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boards: openhwgroup: add CV64A6 on GenesysII board
Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Signed-off-by: Eric Ackermann <[email protected]>
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‎boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV64A6_GENESYSII
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select SOC_CV64A6
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select SOC_SERIES_CV64A6_PROVIDE_FPGA_POWEROFF

‎boards/openhwgroup/cv64a6_genesysII/board.cmake‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
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board_runner_args(openocd "--use-elf")
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board_runner_args(openocd "--verify")
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board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/openhwgroup/cv64a6_genesysII/board.yml‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv64a6_genesysII
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vendor: openhwgroup
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socs:
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- name: cv64a6

‎boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts‎

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/*
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* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv64a6.dtsi>
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/ {
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model = "Openhardwaregroup CV64A6 on Genesys II";
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compatible = "ariane,cv64a6_genesysII";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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// these devices are missing in the Northcape board
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eth: lowrisc-eth@30000000 {
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compatible = "lowrisc-eth";
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device_type = "network";
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interrupt-parent = <&PLIC0>;
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interrupts = <3 0>;
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local-mac-address = [00 18 3e 02 e3 7f];
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reg = <0x0 0x30000000 0x0 0x8000>;
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};
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xlnx_gpio: gpio@40000000 {
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#gpio-cells = <2>;
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compatible = "xlnx,xps-gpio-1.00.a";
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gpio-controller ;
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reg = <0x0 0x40000000 0x0 0x10000 >;
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xlnx,all-inputs = <0x0>;
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xlnx,all-inputs-2 = <0x0>;
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xlnx,dout-default = <0x0>;
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xlnx,dout-default-2 = <0x0>;
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xlnx,gpio-width = <0x8>;
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xlnx,gpio2-width = <0x8>;
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xlnx,interrupt-present = <0x0>;
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xlnx,is-dual = <0x1>;
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xlnx,tri-default = <0xffffffff>;
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xlnx,tri-default-2 = <0xffffffff>;
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};
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};
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&uart0 {
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status = "okay";
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// different interrupt than the CISPA version of the SoC
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interrupts = <1>;
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};
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&spi0 {
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status = "okay";
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// different interrupt than the CISPA version of the SoC
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interrupts = <2 2>;
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};
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&clint{
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status = "okay";
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};
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&dma0 {
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status = "disabled";
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};
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&mdio0{
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status = "disabled";
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};
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&eth0 {
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status = "disabled";
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};

‎boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_BASE64=y
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
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CONFIG_CONSOLE_HANDLER=y
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CONFIG_XIP=n
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CONFIG_INIT_STACKS=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
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CONFIG_FPU=y
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CONFIG_POWEROFF=y
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# RNG
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CONFIG_TIMER_RANDOM_GENERATOR=y
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CONFIG_TEST_RANDOM_GENERATOR=y
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# IRQs
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CONFIG_MULTI_LEVEL_INTERRUPTS=y
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CONFIG_2ND_LEVEL_INTERRUPTS=y
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# 1 PLIC
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
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CONFIG_1ST_LEVEL_INTERRUPT_BITS=7
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CONFIG_2ND_LEVEL_INTERRUPT_BITS=23
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CONFIG_PLIC=y
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CONFIG_3RD_LEVEL_INTERRUPTS=n
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CONFIG_3RD_LEVEL_INTERRUPT_BITS=0
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# no networking support on this board
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# required for the DMA, as no cache coherency in this configuration
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CONFIG_SOC_SERIES_CV64A6_PROVIDE_NONSTANDARD_CACHE_OPTIONS=y
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CONFIG_DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS=y
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# logging
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CONFIG_LOG=y
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CONFIG_LOG_DEFAULT_LEVEL=3
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CONFIG_THREAD_NAME=y
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# increased stack sizes
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CONFIG_ISR_STACK_SIZE=524288
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CONFIG_MAIN_STACK_SIZE=524288
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CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288
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CONFIG_IDLE_STACK_SIZE=524288
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CONFIG_NET_TCP_WORKQ_STACK_SIZE=524288
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CONFIG_NET_TX_STACK_SIZE=524288
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CONFIG_NET_RX_STACK_SIZE=524288
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CONFIG_NET_MGMT_EVENT_STACK_SIZE=524288

‎boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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# Based on the ariane.cfg from the cva6 project:
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# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg
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adapter_khz 1000
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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# Channel 1 is taken by Xilinx JTAG
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ftdi_channel 0
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# links:
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# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
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#
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# Bit MPSSE FT2232 JTAG Type Description
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# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
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# Bit1 TDI ADBUS1 TDI Out Serial Data Out
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# Bit2 TDO ADBUS2 TDO In Serial Data In
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# Bit3 TMS ADBUS3 TMS Out Select Signal Out
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# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
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# this corresponds to the following in/out layout, with TMS initially set to 1
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ftdi_layout_init 0x0018 0x001b
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# we only have to specify nTRST, the others are assigned correctly by default
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ftdi_layout_signal nTRST -ndata 0x0010
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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riscv set_reset_timeout_sec 120
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riscv set_command_timeout_sec 120
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# prefer to use sba for system bus access
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riscv set_prefer_sba off
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# Try enabling address translation (only works for newer versions)
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if { [catch {riscv set_enable_virtual on} ] } {
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echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
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init
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halt
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echo "Ready for Remote Connections"

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