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sreeramIfxfabiobaltieri
sreeramIfx
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fabiobaltieri
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drivers: Implement initial version of ifx_cat1 pdl clock_control
- Shift ifx_cat1 clock_control driver to using pdl instead of hal calls - add soc.c file containing call to SystemInit() - Update board's dts files - add binding for peri divs - update system_clocks.dtsi for psc3 - add new peri clock_control driver Signed-off-by: Sreeram Tatapudi <[email protected]>
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15 files changed

+1142
-23
lines changed

15 files changed

+1142
-23
lines changed

‎boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@ uart1: &scb3 {
3030
status = "okay";
3131
current-speed = <115200>;
3232

33+
clocks = <&peri0_group4_8bit_0>;
34+
3335
pinctrl-0 = <&p6_3_scb3_uart_tx &p6_2_scb3_uart_rx &p6_1_scb3_uart_rts &p6_0_scb3_uart_cts>;
3436
pinctrl-names = "default";
3537
};
@@ -39,7 +41,7 @@ uart1: &scb3 {
3941
};
4042

4143
&path_mux1 {
42-
status = "okay";
44+
status = "disabled";
4345
};
4446

4547
&path_mux2 {
@@ -52,15 +54,15 @@ uart1: &scb3 {
5254

5355
&clk_hf0 {
5456
status = "okay";
55-
clocks = <&fll0>;
5657
};
5758

5859
&clk_hf1 {
59-
status = "okay";
60+
status = "disabled";
6061
};
6162

6263
&clk_hf2 {
6364
status = "okay";
65+
clocks = <&fll0>;
6466
};
6567

6668
&clk_hf3 {

‎boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_defconfig

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,3 +10,6 @@ CONFIG_TRUSTED_EXECUTION_SECURE=y
1010

1111
# Enable GPIO driver
1212
CONFIG_GPIO=y
13+
14+
# Enable clock controller
15+
CONFIG_CLOCK_CONTROL=y

‎boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns_defconfig

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,6 @@ CONFIG_TRUSTED_EXECUTION_NONSECURE=y
1111

1212
# Enable GPIO driver
1313
CONFIG_GPIO=y
14+
15+
# Enable clock controller
16+
CONFIG_CLOCK_CONTROL=y

‎drivers/clock_control/CMakeLists.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,9 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_cont
2626
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)
2727
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
2828
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c)
29+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK clock_control_ifx_cat1_fixed_clock.c)
30+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK clock_control_ifx_cat1_fixed_factor_clock.c)
31+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK clock_control_ifx_cat1_peri_clock.c)
2932
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c)
3033
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_pmc.c)
3134
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5 clock_control_sama7g5_sckc.c)

‎drivers/clock_control/Kconfig.ifx_cat1

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,5 +8,30 @@ config CLOCK_CONTROL_INFINEON_CAT1
88
bool "Infineon CAT1 clock control driver"
99
default y
1010
depends on SOC_FAMILY_INFINEON_CAT1
11+
depends on DT_HAS_FIXED_CLOCK_ENABLED
1112
help
1213
This option enables the clock control driver for Infineon CAT1 family.
14+
15+
config CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK
16+
bool "Infineon CAT1 Fixed clock driver"
17+
default y
18+
depends on SOC_FAMILY_INFINEON_CAT1
19+
depends on DT_HAS_INFINEON_FIXED_CLOCK_ENABLED
20+
help
21+
This option enables the Fixed clock driver for Infineon CAT1 family.
22+
23+
config CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK
24+
bool "Infineon CAT1 Fixed factor clock driver"
25+
default y
26+
depends on SOC_FAMILY_INFINEON_CAT1
27+
depends on DT_HAS_INFINEON_FIXED_FACTOR_CLOCK_ENABLED
28+
help
29+
This option enables the Fixed clock driver for Infineon CAT1 family.
30+
31+
config CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK
32+
bool "Infineon CAT1 Fixed clock driver"
33+
default y
34+
depends on SOC_FAMILY_INFINEON_CAT1
35+
depends on DT_HAS_INFINEON_CAT1_PERI_DIV_ENABLED
36+
help
37+
This option enables the Peripheral clock driver for Infineon CAT1 family.

‎drivers/clock_control/clock_control_ifx_cat1_fixed_clock.c

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
/*
2+
* Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3+
* an affiliate of Cypress Semiconductor Corporation
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/**
9+
* @brief Clock control driver for Infineon CAT1 MCU family.
10+
*/
11+
12+
#include <zephyr/drivers/clock_control.h>
13+
#include <zephyr/kernel.h>
14+
#include <stdlib.h>
15+
16+
#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
17+
#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
18+
#include <cy_sysclk.h>
19+
20+
#define DT_DRV_COMPAT infineon_fixed_clock
21+
22+
struct fixed_rate_clock_config {
23+
uint32_t rate;
24+
uint32_t id; /* ifx_cat1_clock_block */
25+
};
26+
27+
static int fixed_rate_clk_init(const struct device *dev)
28+
{
29+
const struct fixed_rate_clock_config *const config = dev->config;
30+
31+
switch (config->id) {
32+
33+
case IFX_CAT1_CLOCK_BLOCK_IMO:
34+
break;
35+
36+
case IFX_CAT1_CLOCK_BLOCK_FLL:
37+
break;
38+
39+
case IFX_CAT1_CLOCK_BLOCK_IHO:
40+
Cy_SysClk_IhoEnable();
41+
break;
42+
43+
default:
44+
break;
45+
}
46+
47+
return 0;
48+
}
49+
50+
#define FIXED_CLK_INIT(idx) \
51+
static const struct fixed_rate_clock_config fixed_rate_clock_config_##idx = { \
52+
.rate = DT_INST_PROP(idx, clock_frequency), \
53+
.id = DT_INST_PROP(idx, clock_block), \
54+
}; \
55+
DEVICE_DT_INST_DEFINE(idx, fixed_rate_clk_init, NULL, NULL, \
56+
&fixed_rate_clock_config_##idx, PRE_KERNEL_1, \
57+
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
58+
59+
DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)

‎drivers/clock_control/clock_control_ifx_cat1_fixed_factor_clock.c

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
/*
2+
* Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3+
* an affiliate of Cypress Semiconductor Corporation
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/**
9+
* @brief Clock control driver for Infineon CAT1 MCU family.
10+
*/
11+
12+
#include <zephyr/drivers/clock_control.h>
13+
#include <zephyr/kernel.h>
14+
#include <stdlib.h>
15+
16+
#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
17+
#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
18+
#include <cy_sysclk.h>
19+
20+
#define DT_DRV_COMPAT infineon_fixed_factor_clock
21+
22+
struct fixed_factor_clock_config {
23+
uint32_t divider;
24+
uint32_t block; /* ifx_cat1_clock_block */
25+
uint32_t instance;
26+
uint32_t source_path;
27+
uint32_t source_instance;
28+
};
29+
30+
static int fixed_factor_clk_init(const struct device *dev)
31+
{
32+
const struct fixed_factor_clock_config *const config = dev->config;
33+
34+
switch (config->block) {
35+
36+
case IFX_CAT1_CLOCK_BLOCK_PATHMUX:
37+
Cy_SysClk_ClkPathSetSource(config->instance, config->source_path);
38+
break;
39+
40+
case IFX_CAT1_CLOCK_BLOCK_HF:
41+
Cy_SysClk_ClkHfSetSource(config->instance, config->source_instance);
42+
Cy_SysClk_ClkHfSetDivider(config->instance, config->divider);
43+
Cy_SysClk_ClkHfEnable(config->instance);
44+
break;
45+
46+
default:
47+
return -EINVAL;
48+
}
49+
50+
return 0;
51+
}
52+
53+
#define FIXED_CLK_INIT(idx) \
54+
static const struct fixed_factor_clock_config fixed_factor_clock_config_##idx = { \
55+
.divider = DT_INST_PROP_OR(idx, clock_divider, 1u), \
56+
.block = DT_INST_PROP(idx, clock_block), \
57+
.instance = DT_INST_PROP(idx, clock_instance), \
58+
.source_path = DT_INST_PROP_OR(idx, source_path, 1u), \
59+
.source_instance = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_instance), \
60+
}; \
61+
DEVICE_DT_INST_DEFINE(idx, fixed_factor_clk_init, NULL, NULL, \
62+
&fixed_factor_clock_config_##idx, PRE_KERNEL_1, \
63+
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
64+
65+
DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)

‎drivers/clock_control/clock_control_ifx_cat1_peri_clock.c

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
/*
2+
* Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3+
* an affiliate of Cypress Semiconductor Corporation
4+
*
5+
* SPDX-License-Identifier: Apache-2.0
6+
*/
7+
8+
/**
9+
* @brief Peripheral Clock control driver for Infineon CAT1 MCU family.
10+
*/
11+
12+
#define DT_DRV_COMPAT infineon_cat1_peri_div
13+
14+
#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
15+
#include <zephyr/drivers/clock_control.h>
16+
#include <zephyr/kernel.h>
17+
#include <stdlib.h>
18+
#include <cy_sysclk.h>
19+
#include <cy_systick.h>
20+
21+
struct ifx_cat1_peri_clock_data {
22+
struct ifx_cat1_resource_inst hw_resource;
23+
struct ifx_cat1_clock clock;
24+
uint16_t divider;
25+
CySCB_Type *reg_addr;
26+
};
27+
28+
#if defined(CY_IP_MXPERI) || defined(CY_IP_M0S8PERI)
29+
30+
#define _IFX_CAT1_PCLK_GROUP(clkdst) 0
31+
#define _IFX_CAT1_TCPWM0_PCLK_CLOCK0 PCLK_TCPWM0_CLOCKS0
32+
#define _IFX_CAT1_TCPWM1_PCLK_CLOCK0 PCLK_TCPWM1_CLOCKS0
33+
#define _IFX_CAT1_SCB0_PCLK_CLOCK PCLK_SCB0_CLOCK
34+
35+
#elif defined(CY_IP_MXSPERI)
36+
37+
#define _IFX_CAT1_PCLK_GROUP(clkdst) ((uint8_t)((uint32_t)(clkdst) >> 8))
38+
#define _IFX_CAT1_TCPWM0_PCLK_CLOCK0 PCLK_TCPWM0_CLOCK_COUNTER_EN0
39+
#define _IFX_CAT1_TCPWM1_PCLK_CLOCK0 PCLK_TCPWM1_CLOCK_COUNTER_EN0
40+
#define _IFX_CAT1_SCB0_PCLK_CLOCK PCLK_SCB0_CLOCK_SCB_EN
41+
#define _IFX_CAT1_SCB1_PCLK_CLOCK PCLK_SCB1_CLOCK_SCB_EN
42+
#define _IFX_CAT1_SCB5_PCLK_CLOCK PCLK_SCB5_CLOCK_SCB_EN
43+
#endif
44+
45+
en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num)
46+
{
47+
en_clk_dst_t clk;
48+
/* PSOC6A256K does not have SCB 3 */
49+
#if defined(CY_DEVICE_PSOC6A256K)
50+
if (block_num < 3) {
51+
clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num);
52+
} else {
53+
clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num - 1);
54+
}
55+
#else
56+
clk = (en_clk_dst_t)((uint32_t)_IFX_CAT1_SCB0_PCLK_CLOCK + block_num);
57+
#endif
58+
return clk;
59+
}
60+
61+
static int ifx_cat1_peri_clock_init(const struct device *dev)
62+
{
63+
struct ifx_cat1_peri_clock_data *const data = dev->data;
64+
65+
en_clk_dst_t clk_idx = ifx_cat1_scb_get_clock_index(data->hw_resource.block_num);
66+
67+
ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1);
68+
ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock);
69+
ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock);
70+
71+
return 0;
72+
}
73+
74+
#define INFINEON_CAT1_PERI_CLOCK_INIT(n) \
75+
static struct ifx_cat1_peri_clock_data ifx_cat1_peri_clock##n##_data = { \
76+
.clock = \
77+
{ \
78+
.block = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
79+
DT_INST_PROP_BY_IDX(n, clk_dst, 1), \
80+
DT_INST_PROP(n, div_type)), \
81+
.channel = DT_INST_PROP(n, div_num), \
82+
}, \
83+
.divider = DT_INST_PROP(n, div_value), \
84+
.hw_resource = {.type = IFX_CAT1_RSC_SCB, \
85+
.block_num = DT_INST_PROP(n, scb_block)}, \
86+
}; \
87+
\
88+
DEVICE_DT_INST_DEFINE(n, &ifx_cat1_peri_clock_init, NULL, &ifx_cat1_peri_clock##n##_data, \
89+
NULL, PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
90+
91+
DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_PERI_CLOCK_INIT)

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