boards: arm: mimxrt595_evk: add configuration for RM68200 display

Add configuration for RM68200 MIPI display. This display
controller drives a 1280x720 LCD display.

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

boards/arm/mimxrt595_evk/Kconfig.defconfig

@@ -1,6 +1,6 @@
 # MIMXRT595-EVK board
 
-# Copyright (c) 2022, NXP
+# Copyright 2022-2023, NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_MIMXRT595_EVK
@@ -29,4 +29,44 @@ config HEAP_MEM_POOL_SIZE
 
 endif # DMA_MCUX_LPC
 
+if DISPLAY
+
+# Enable MIPI display driver
+
+config MIPI_DSI
+	default y
+
+# Use external framebuffer memory for the LCDIF framebuffer
+config MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
+	default y
+# Use FlexSPI2 base address for framebuffer (pSRAM is present on this bus)
+config MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR
+	default 0x38000000
+# M33 core and LCDIF both access FlexSPI2 through the same cache,
+# so coherency does not need to be managed.
+config MCUX_DCNANO_LCDIF_MAINTAIN_CACHE
+	depends on !MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
+
+endif # DISPLAY
+
+config KSCAN
+	default y if LVGL
+
+if LVGL
+
+config LV_Z_POINTER_KSCAN
+	default y
+
+config LV_Z_VDB_SIZE
+	default 16
+
+config LV_Z_DPI
+	default 128
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+endchoice
+
+endif # LVGL
+
 endif # BOARD_MIMXRT595_EVK

boards/arm/mimxrt595_evk/doc/index.rst

@@ -105,6 +105,10 @@ already supported, which can also be re-used on this mimxrt595_evk board:
 +-----------+------------+-------------------------------------+
 | SDHC      | on-chip    | disk access (works with eMMC & SD)  |
 +-----------+------------+-------------------------------------+
+| DISPLAY   | on-chip    | LCDIF; MIPI-DSI. Tested with RM68200|
+|           |            | based MIPI display                  |
+|           |            | (`RK055HDMIPI4M`_)                  |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 
@@ -293,3 +297,6 @@ steps:
 
 .. _i.MX RT595 Reference Manual:
    https://www.nxp.com/webapp/Download?colCode=IMXRT500RM
+
+.. _RK055HDMIPI4M:
+   https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/5-5-lcd-panel:RK055HDMIPI4M

boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022, NXP
+ * Copyright 2022-2023, NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,7 @@
 		magn0 = &fxos8700;
 		accel0 = &fxos8700;
 		sdhc0 = &usdhc0;
+		kscan0 = &touch_controller;
 	};
 
 	chosen {
@@ -34,6 +35,8 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &flexcomm0;
 		zephyr,shell-uart = &flexcomm0;
+		zephyr,display = &lcdif;
+		zephyr,keyboard-scan = &touch_controller;
 	};
 
 	gpio_keys {
@@ -123,6 +126,13 @@
 		 * this state.
 		 */
 	};
+
+	en_mipi_display: enable-mipi-display {
+		compatible = "regulator-fixed";
+		regulator-name = "en_mipi_display";
+		enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+	};
 };
 
 &cpu0 {
@@ -142,6 +152,45 @@
 	status = "okay";
 };
 
+&lcdif {
+	status = "okay";
+	width = <720>;
+	height = <1280>;
+	clk-div = <7>;
+	polarity = <12>;
+	hsync = <8>;
+	hfp = <32>;
+	hbp = <32>;
+	vsync = <2>;
+	vfp = <16>;
+	vbp = <14>;
+	backlight-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+	data-bus-width = "24-bit";
+	pixel-format = "rgb-565";
+};
+
+&mipi_dsi {
+	status = "okay";
+	nxp,lcdif = <&lcdif>;
+	dpi-color-coding = "24-bit";
+	dpi-pixel-packet = "24-bit";
+	dpi-video-mode = "burst";
+	dpi-bllp-mode = "low-power";
+	autoinsert-eotp;
+	dphy-clk-div = <12>;
+
+	rm68200@0 {
+		status = "okay";
+		compatible = "raydium,rm68200";
+		reg = <0x0>;
+		reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+		data-lanes = <2>;
+		width = <720>;
+		height = <1280>;
+		pixel-format = <MIPI_DSI_PIXFMT_RGB565>;
+	};
+};
+
 &flexcomm0 {
 	compatible = "nxp,lpc-usart";
 	status = "okay";
@@ -165,6 +214,13 @@ arduino_i2c: &flexcomm4 {
 		int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
 		reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 	};
+
+	touch_controller: gt911@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+		irq-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 hs_spi1: &hs_lspi1 {
@@ -380,6 +436,10 @@ zephyr_udc0: &usbhs {
 	};
 };
 
+/*
+ * Configure FlexSPI2 to use 1KB of AHB RX buffer for GPU/Display master.
+ * This will improve performance when using external pSRAM with the LCDIF.
+ */
 &flexspi2 {
 	status = "okay";
 	pinctrl-0 = <&pinmux_flexspi2>;
@@ -389,6 +449,7 @@ zephyr_udc0: &usbhs {
 	ahb-bufferable;
 	ahb-cacheable;
 	ahb-read-addr-opt;
+	rx-buffer-config = <1 7 11 1024>;
 	aps6408l: aps6408l@0 {
 		compatible = "nxp,imx-flexspi-aps6408l";
 		/* APS6408L is 8MB, 64MBit pSRAM */