mec150x: clk ctrl: fix clock trim register update

jvasanth1 · galak · commit 6bd7f781a33c · 2023-01-19T12:45:56.000-06:00
Program the right trim control register for mec150x.
This fixes uart debug console output issue.

Signed-off-by: Jay Vasanth &lt;jay.vasanth@microchip.com&gt;
diff --git a/drivers/clock_control/clock_control_mchp_xec.c b/drivers/clock_control/clock_control_mchp_xec.c
@@ -131,6 +131,8 @@ struct vbatr_hw_regs {
 	volatile uint32_t CLK32_SRC;
 	uint32_t RSVD2[2];
 	volatile uint32_t CLK32_TRIM;
+	uint32_t RSVD3[1];
+	volatile uint32_t CLK32_TRIM_CTRL;
 };
 
 /* MEC152x VBAT CLK32_SRC register defines */
@@ -279,7 +281,7 @@ static int soc_clk32_init(const struct device *dev,
 
 	if (MCHP_DEVICE_ID() == XEC_CC15_GCFG_DID_DEV_ID_MEC150x) {
 		if (MCHP_REVISION_ID() == MCHP_GCFG_REV_B0) {
-			vbr->CLK32_TRIM = XEC_CC15_TRIM_ENABLE_INT_OSCILLATOR;
+			vbr->CLK32_TRIM_CTRL = XEC_CC15_TRIM_ENABLE_INT_OSCILLATOR;
 		}
 	}
 

Original file line number	Diff line number	Diff line change
`@@ -131,6 +131,8 @@ struct vbatr_hw_regs {`
`131`	`131`	`volatile uint32_t CLK32_SRC;`
`132`	`132`	`uint32_t RSVD2[2];`
`133`	`133`	`volatile uint32_t CLK32_TRIM;`
	`134`	`+ uint32_t RSVD3[1];`
	`135`	`+ volatile uint32_t CLK32_TRIM_CTRL;`
`134`	`136`	`};`
`135`	`137`
`136`	`138`	`/* MEC152x VBAT CLK32_SRC register defines */`
`@@ -279,7 +281,7 @@ static int soc_clk32_init(const struct device *dev,`
`279`	`281`
`280`	`282`	`if (MCHP_DEVICE_ID() == XEC_CC15_GCFG_DID_DEV_ID_MEC150x) {`
`281`	`283`	`if (MCHP_REVISION_ID() == MCHP_GCFG_REV_B0) {`
`282`		`- vbr->CLK32_TRIM = XEC_CC15_TRIM_ENABLE_INT_OSCILLATOR;`
	`284`	`+ vbr->CLK32_TRIM_CTRL = XEC_CC15_TRIM_ENABLE_INT_OSCILLATOR;`
`283`	`285`	`}`
`284`	`286`	`}`
`285`	`287`