drivers: clock_control: stm32: Fixed domain clock configuration

In some case, we may need to describe a domain clock for a device
while there is no way to configure it (ex: USB clock set on PLL_Q output
on F405 devices > It is not selectable).
Then, configuring a device clock domain in the clock_control driver
will allow to retrieve its subsys rate.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

drivers/clock_control/clock_stm32_ll_common.c

@@ -242,6 +242,11 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return err;
 	}
 
+	if (pclken->enr == NO_SEL) {
+		/* Domain clock is fixed. Nothing to set. Exit */
+		return 0;
+	}
+
 	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
 		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
 

include/zephyr/dt-bindings/clock/stm32f0_clock.h

@@ -73,5 +73,7 @@
 #define USART3_SEL(val)		STM32_CLOCK(val, 3, 18, CFGR3_REG)
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f1_clock.h

@@ -59,5 +59,7 @@
 /** @brief Device domain clocks selection helpers */
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f3_clock.h

@@ -83,5 +83,7 @@
 #define TIM3_4_SEL(val)		STM32_CLOCK(val, 1, 25, CFGR3_REG)
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f4_clock.h

@@ -68,4 +68,7 @@
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
 
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f7_clock.h

@@ -92,5 +92,7 @@
 #define CK48M_SEL(val)		STM32_CLOCK(val, 1, 27, DKCFGR2_REG)
 #define SDMMC1_SEL(val)		STM32_CLOCK(val, 1, 28, DKCFGR2_REG)
 #define SDMMC2_SEL(val)		STM32_CLOCK(val, 1, 29, DKCFGR2_REG)
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32g0_clock.h

@@ -92,7 +92,7 @@
 #define USB_SEL(val)		STM32_CLOCK(val, 3, 12, CCIPR2_REG)
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
-
-
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32g4_clock.h

@@ -95,5 +95,7 @@
 #define QSPI_SEL(val)		STM32_CLOCK(val, 3, 20, CCIPR2_REG)
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32l0_clock.h

@@ -74,5 +74,7 @@
 #define HSI48_SEL(val)		STM32_CLOCK(val, 1, 26, CCIPR_REG)
 /** CSR devices */
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 16, CSR_REG)
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32l1_clock.h

@@ -57,4 +57,7 @@
 
 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 16, CSR_REG)
 
+/** Dummy: Add a specificier when no selection is possible */
+#define NO_SEL			0xFF
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */