arch: arm: cortex_m: scb: use SHPR name for all Cortex-M

CMSIS 5 had a different name for the SHP/SHPR registers depending on which
Cortex-M was used. This inconsistency is fixed in CMSIS 6, which is the new
default for Cortex-M in Zephyr.

Remove the conditional and always use SHPR in the SCB backup/restore code.

Signed-off-by: Mathieu Choplain <[email protected]>

Author: mathieuchopstm

arch/arm/core/cortex_m/scb.c

@@ -25,20 +25,6 @@
 #include <zephyr/arch/cache.h>
 #include <zephyr/arch/arm/cortex_m/scb.h>
 
-/* For historical reasons, in Cortex-M family, CMSIS code calls System Handler Priority
- * register SHP or SHPR. This code defines the name of the register
- * according to the specific Cortex-M variant.
- */
-#if defined(CONFIG_CPU_CORTEX_M0)  || \
-	defined(CONFIG_CPU_CORTEX_M0PLUS)  || \
-	defined(CONFIG_CPU_CORTEX_M1)  || \
-	defined(CONFIG_CPU_CORTEX_M3) || \
-	defined(CONFIG_CPU_CORTEX_M4)
-#define SHPR_FIELD_NAME SHP
-#else
-#define SHPR_FIELD_NAME SHPR
-#endif
-
 #if defined(CONFIG_CPU_HAS_NXP_SYSMPU)
 #include <fsl_sysmpu.h>
 #endif
@@ -191,7 +177,7 @@ void z_arm_save_scb_context(struct scb_context *context)
 	context->ccr   = SCB->CCR;
 
 	/* Backup System Handler Priority Registers */
-	volatile uint32_t *shpr = (volatile uint32_t *) SCB->SHPR_FIELD_NAME;
+	volatile uint32_t *shpr = (volatile uint32_t *)SCB->SHPR;
 
 	for (int i = 0; i < SHPR_SIZE_W; i++) {
 		context->shpr[i] = shpr[i];