Revert "soc: riscv-privileged: support SoCs without reset vector"

ycsin · aescolar · commit 6de21fc1d2ad · 2024-07-02T09:24:44.000+02:00
This reverts commit 75f5d98. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
diff --git a/soc/common/riscv-privileged/vector.S b/soc/common/riscv-privileged/vector.S
@@ -103,10 +103,5 @@ SECTION_FUNC(vectors, __start)
 
 #endif /* CONFIG_RISCV_VECTORED_MODE */
 
-#if CONFIG_INCLUDE_RESET_VECTOR
 	/* Jump to __reset */
 	tail __reset
-#else
-	/* Jump to __initialize */
-	tail __initialize
-#endif
