boards: renesas: ek_ra8p1: enable ArduCam CU450 OV5640 shield

Update the EK-RA8P1 board to support the ArduCam CU450 OV5640 shield:

- Update pinctrl definitions in ek_ra8p1-pinctrl.dtsi
- Update board DTS in ek_ra8p1_r7ka8p1kflcac_cm85.dts
- Add board-specific overlay for the shield
- Update documentation

Signed-off-by: Khanh Nguyen <[email protected]>

Author: KhanhNguyen-RVC

boards/renesas/ek_ra8p1/doc/index.rst

@@ -87,7 +87,13 @@ Supported Features
 
 .. note::
 
-   - Other hardware features are currently not supported by the port.
+   - For using the Camera Expansion Port (J35) in DVP interface, please set switch SW4 as following configuration:
+
+     +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+
+     | SW4-1 PMOD1 | SW4-2 PMOD1 | SW4-3 Octo-SPI | SW4-4 Arduino | SW4-5 I3C | SW4-6 MIPI | SW4-7 USBFS | SW4-8 USBHS |
+     +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+
+     |     OFF     |     OFF     |      OFF       |     OFF       |     OFF   |     ON     |     OFF     |    OFF      |
+     +-------------+-------------+----------------+---------------+-----------+------------+-------------+-------------+
 
 Dual Core Operation
 *******************

boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi

@@ -62,6 +62,14 @@
 		};
 	};
 
+	pwm12_default: pwm12_default {
+		group1 {
+			/* GTIOC12A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 5, 1)>;
+			drive-strength = "medium";
+		};
+	};
+
 	iic1_default: iic1_default {
 		group1 {
 			/* SCL1 SDA1*/
@@ -71,6 +79,22 @@
 		};
 	};
 
+	ceu_default: ceu_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_CEU, 4, 0)>, /* VIO_D0 */
+				<RA_PSEL(RA_PSEL_CEU, 9, 2)>, /* VIO_D1 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 5)>, /* VIO_D2 */
+				<RA_PSEL(RA_PSEL_CEU, 4, 6)>, /* VIO_D3 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 0)>, /* VIO_D4 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 1)>, /* VIO_D5 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 2)>, /* VIO_D6 */
+				<RA_PSEL(RA_PSEL_CEU, 7, 3)>, /* VIO_D7 */
+				<RA_PSEL(RA_PSEL_CEU, 11, 4)>, /* VIO_CLK */
+				<RA_PSEL(RA_PSEL_CEU, 11, 3)>, /* VIO_HD */
+				<RA_PSEL(RA_PSEL_CEU, 11, 2)>; /* VIO_VD */
+		};
+	};
+
 	sdram_default: sdram_default {
 		group1 {
 			psels = <RA_PSEL(RA_PSEL_BUS, 10, 3)>, /* SDRAM_A2 */

boards/renesas/ek_ra8p1/ek_ra8p1.dtsi

@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/gpio/arducam-ffc-40pin-connector.h>
 #include <dt-bindings/input/input-event-codes.h>
 #include "ek_ra8p1-pinctrl.dtsi"
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
@@ -54,6 +55,14 @@
 		zephyr,memory-region = "SDRAM";
 		status = "okay";
 	};
+
+	arducam_ffc_40pin_connector: arducam-ffc-40pin-connector {
+		compatible = "arducam,ffc-40pin-connector";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0x0 0x3f>;
+		gpio-map = <ARDUCAM_FFC_40PIN_RESET 0 &ioport7 9 0>;
+	};
 };
 
 &xtal {

boards/renesas/ek_ra8p1/ek_ra8p1_r7ka8p1kflcac_cm85.dts

@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <renesas/ra/ra8/r7ka8p1kflcac_cm85.dtsi>
+#include <zephyr/dt-bindings/pwm/pwm.h>
 #include "ek_ra8p1.dtsi"
 
 / {
@@ -105,6 +106,36 @@
 	};
 };
 
+&pwm12 {
+	pinctrl-0 = <&pwm12_default>;
+	interrupts = <20 1>, <21 1>;
+	interrupt-names = "gtioca", "overflow";
+	pinctrl-names = "default";
+
+	cam_clock: pwmclock {
+		compatible = "pwm-clock";
+		status = "disabled";
+		#clock-cells = <1>;
+		pwms = <&pwm12 0 PWM_KHZ(12000) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&ceu {
+	pinctrl-0 = <&ceu_default>;
+	pinctrl-names = "default";
+	interrupts = <22 1>;
+	interrupt-names = "ceui";
+	clocks = <&pclka MSTPC 16>, <&cam_clock 0>;
+	clock-names = "pclk", "cam-xclk";
+	burst-transfer = <256>;
+};
+
 zephyr_lcdif: &lcdif {};
 
 pmod_sd_shield: &sdhc0 {};
+
+arducam_ffc_40pin_i2c: &iic1 {};
+
+arducam_ffc_40pin_dvp_interface: &ceu {};
+
+arducam_ffc_40pin_dvp_xclk: &cam_clock {};

boards/shields/arducam_cu450_ov5640/boards/ek_ra8p1_r7ka8p1kflcac_cm85.overlay

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pwm12 {
+	status = "okay";
+};
+
+&arducam_ffc_40pin_i2c {
+	clock-frequency = <DT_FREQ_K(100)>;
+};
+
+&arducam_ffc_40pin_dvp_xclk {
+	clock-frequency = <DT_FREQ_M(12)>;
+	status = "okay";
+};
+
+&arducam_ffc_40pin_dvp_interface {
+	swap-8bits;
+	swap-16bits;
+	swap-32bits;
+
+	port {
+		dvp_ffc40_ep_in: endpoint {
+			hsync-sample = <1>;
+			vsync-sample = <1>;
+		};
+	};
+};