benchmarking: remove execution benchmarking code

This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.

For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.

Furthermore, much of the assembly code used had issues.

Signed-off-by: Anas Nashif <[email protected]>
Signed-off-by: Daniel Leung <[email protected]>

Author: nashif

arch/arc/core/isr_wrapper.S

@@ -275,10 +275,6 @@ SECTION_FUNC(TEXT, _isr_demux)
 	push r59
 #endif
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	bl read_timer_start_of_isr
-#endif
-
 #if defined(CONFIG_TRACING_ISR)
 	bl sys_trace_isr_enter
 #endif
@@ -299,13 +295,6 @@ irq_hint_handled:
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
 	ld_s r1, [r0, 4] /* ISR into r1 */
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push_s r0
-	push_s r1
-	bl read_timer_end_of_isr
-	pop_s r1
-	pop_s r0
-#endif
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 

arch/arc/core/switch.S

@@ -54,17 +54,6 @@ GTEXT(z_arc_switch)
 
 SECTION_FUNC(TEXT, z_arc_switch)
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push_s r0
-	push_s r1
-	push_s blink
-
-	bl read_timer_start_of_swap
-
-	pop_s blink
-	pop_s r1
-	pop_s r0
-#endif
 	/*
 	 * r0 = new_thread->switch_handle = switch_to thread,
 	 * r1 = &old_thread->switch_handle
@@ -125,13 +114,6 @@ _switch_return_from_coop:
 	pop_s r3    /* status32 into r3 */
 	kflag r3    /* write status32 */
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push_s blink
-
-	bl read_timer_end_of_swap
-
-	pop_s blink
-#endif /* CONFIG_EXECUTION_BENCHMARKING */
 #ifdef CONFIG_TRACING
 	push_s blink
 

arch/arc/core/userspace.S

@@ -179,10 +179,6 @@ _arc_go_to_user_space:
 	mov r30, 0
 	mov blink, 0
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	bl read_timer_end_of_userspace_enter
-#endif
-
 	rtie
 
 /**

arch/arm/core/aarch32/isr_wrapper.S

@@ -80,10 +80,6 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 	str r0, [r2, #_kernel_offset_to_nested]
 #endif /* CONFIG_CPU_CORTEX_M */
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	bl read_timer_start_of_isr
-#endif
-
 #ifdef CONFIG_TRACING_ISR
 	bl sys_trace_isr_enter
 #endif
@@ -187,11 +183,6 @@ _idle_state_cleared:
 			 * in thumb mode */
 
 	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	push {r0, r3}	/* Save r0 and r3 into stack */
-	bl read_timer_end_of_isr
-	pop {r0, r3}	/* Restore r0 and r3 regs */
-#endif /* CONFIG_EXECUTION_BENCHMARKING */
 	blx r3		/* call ISR */
 
 #if defined(CONFIG_CPU_CORTEX_R)

arch/arm/core/aarch32/swap.c

@@ -7,9 +7,6 @@
 #include <kernel.h>
 #include <kernel_internal.h>
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-extern void read_timer_start_of_swap(void);
-#endif
 extern const int _k_neg_eagain;
 
 /* The 'key' actually represents the BASEPRI register
@@ -35,10 +32,6 @@ extern const int _k_neg_eagain;
  */
 int arch_swap(unsigned int key)
 {
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	read_timer_start_of_swap();
-#endif
-
 	/* store off key and return value */
 	_current->arch.basepri = key;
 	_current->arch.swap_return_value = _k_neg_eagain;

arch/arm/core/aarch32/swap_helper.S

@@ -337,18 +337,6 @@ _thread_irq_disabled:
     pop {r2, lr}
 #endif /* CONFIG_BUILTIN_STACK_GUARD */
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-    push {r0, lr}
-    bl read_timer_end_of_swap
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    pop {r0, r1}
-    mov lr,r1
-#else
-    pop {r0, lr}
-#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
-
-#endif /* CONFIG_EXECUTION_BENCHMARKING */
-
 #ifdef CONFIG_TRACING
     /* Register the context switch */
     push {r0, lr}

arch/arm/core/aarch32/userspace.S

@@ -216,20 +216,6 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
     /* restore r0 */
     mov r0, lr
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-    stm sp!,{r0-r3} /* Save regs r0 to r4 on stack */
-    push {r0, lr}
-    bl read_timer_end_of_userspace_enter
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-    pop {r0, r3}
-    mov lr,r3
-#else
-    pop {r0, lr}
-#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
-    ldm sp!,{r0-r3} /* Restore r0 to r3 regs */
-
-#endif /* CONFIG_EXECUTION_BENCHMARKING */
-
     /* change processor mode to unprivileged */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     push {r0, r1, r2, r3}

arch/common/CMakeLists.txt

@@ -1,17 +1,12 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_GEN_ISR_TABLES OR CONFIG_EXECUTION_BENCHMARKING)
+if(CONFIG_GEN_ISR_TABLES)
   zephyr_library()
 
   zephyr_library_sources_ifdef(
     CONFIG_GEN_ISR_TABLES
     sw_isr_common.c
     )
-
-  zephyr_library_sources_ifdef(
-    CONFIG_EXECUTION_BENCHMARKING
-    timing_info_bench.c
-    )
 endif()
 
 if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND

arch/common/timing_info_bench.c

@@ -80,11 +80,6 @@ void _enter_irq(uint32_t ipending)
 {
 	int index;
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-	extern void read_timer_start_of_isr(void);
-	read_timer_start_of_isr();
-#endif
-
 	_kernel.cpus[0].nested++;
 
 #ifdef CONFIG_IRQ_OFFLOAD
@@ -103,10 +98,6 @@ void _enter_irq(uint32_t ipending)
 
 		ite = &_sw_isr_table[index];
 
-#ifdef CONFIG_EXECUTION_BENCHMARKING
-		extern void read_timer_end_of_isr(void);
-		read_timer_end_of_isr();
-#endif
 		ite->isr(ite->arg);
 #ifdef CONFIG_TRACING_ISR
 		sys_trace_isr_exit();