drivers: gpio: Enable support for latest GINF method

Enable support for latest GINF method which requires 3 paramters
for each GPIO group and enables gpio support for intel_ptl_h
platform.

Signed-off-by: Anisetti Avinash Krishna <[email protected]>

Author: akanisetti

drivers/gpio/gpio_intel.c

@@ -120,28 +120,42 @@ struct gpio_intel_data {
 	uint32_t pad_owner_reg;
 	uint32_t host_owner_reg;
 	uint32_t intr_stat_reg;
+	uint32_t intr_en_reg;
 	uint32_t base_num;
 #endif
 };
 
 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
+#define GPIO_PAD_OWNERSHIP_SHIFT (0x04) /* Shift between Ownership regs */
+
+#define GPIO_PAD_PINS_PER_REG (8) /*Pins for each Register */
+
 #define GPIO_REG_BASE_GET(dev) DEVICE_MMIO_NAMED_GET(dev, reg_base)
 
 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
 
-#define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
-
 #define PIN_OFFSET_GET(dev) (0)
 
-#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
-
 #define REG_PAD_HOST_SW_OWNER_GET(data) (data)->host_owner_reg
 
 #define GPIO_BASE_GET(cdf) (0)
 
 #define GPIO_INTERRUPT_BASE_GET(cfg) (0)
 
 #define GPIO_GET_PIN_MAX(dev) ((struct gpio_intel_data *)(dev)->data)->num_pins
+
+#define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_en_reg
+
+#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(acpi_ginf)
+#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset)\
+	(data)->pad_owner_reg + (pin * GPIO_PAD_OWNERSHIP_SHIFT)
+
+#else
+#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg +\
+	(((pin) / GPIO_PAD_PINS_PER_REG) * GPIO_PAD_OWNERSHIP_SHIFT)
+
+#endif
+
 #else /* Non-ACPI */
 #define GPIO_REG_BASE_GET(dev) GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base))
 
@@ -564,13 +578,14 @@ static DEVICE_API(gpio, gpio_intel_api) = {
 /* We need support either DTS or ACPI base resource enumeration at time.*/
 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
 
-static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hid, char *uid)
+static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hid, char *uid,
+				bool ginf)
 {
 	int ret;
 	struct gpio_acpi_res res;
 	struct gpio_intel_data *data = dev->data;
 
-	ret = soc_acpi_gpio_resource_get(bank_idx, hid, uid, &res);
+	ret = soc_acpi_gpio_resource_get(bank_idx, hid, uid, &res, ginf);
 	if (ret) {
 		return ret;
 	}
@@ -580,7 +595,8 @@ static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hi
 	data->num_pins = res.num_pins;
 	data->pad_owner_reg = res.pad_owner_reg;
 	data->host_owner_reg = res.host_owner_reg;
-	data->intr_stat_reg = res.intr_stat_reg;
+	data->intr_stat_reg = res.gp_evt_stat_reg - DT_INST_PROP(0, int_stat_offset);
+	data->intr_en_reg = res.gp_evt_stat_reg - DT_INST_PROP(0, int_en_offset);
 	data->base_num = res.base_num;
 	data->pad_base = res.pad_base;
 
@@ -605,8 +621,9 @@ static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hi
 #define GPIO_INIT_FN_DEFINE(n)                                                                     \
 	static int gpio_intel_init##n(const struct device *dev)                                    \
 	{                                                                                          \
-		return gpio_intel_acpi_enum(dev, DT_INST_PROP(n, group_index),	\
-			ACPI_DT_HID(DT_DRV_INST(n)),  ACPI_DT_UID(DT_DRV_INST(n)));   \
+		return gpio_intel_acpi_enum(dev, DT_INST_PROP(n, group_index),			   \
+			ACPI_DT_HID(DT_DRV_INST(n)),  ACPI_DT_UID(DT_DRV_INST(n)),		   \
+			DT_INST_PROP(n, acpi_ginf_3_param));					   \
 	}
 
 #define GPIO_MMIO_ROM_INIT(n)

dts/bindings/gpio/intel,gpio.yaml

@@ -25,6 +25,33 @@ properties:
     type: int
     description: Pin offset of this GPIO entry
 
+  int-en-offset:
+    type: int
+    description: |
+      This parameter enables to add proper offset to access
+      GPIO_INT_EN register from General Purpose Events status
+      Register, as it is observed that the offset varies from
+      platform to platform. GP_EVENT_STAT register is fetched
+      from ACPI GPIO table.
+
+  int-stat-offset:
+    type: int
+    description: |
+      This parameter enables to add proper offset to access
+      GPIO_INT_STAT register from General Purpose Events status
+      Register, as it is observed that the offset varies from
+      platform to platform. GP_EVENT_STAT register is fetched
+      from ACPI GPIO table.
+
+  acpi-ginf-3-param:
+    type: boolean
+    description: |
+      This boolean will indicate the version of GINF method ACPI
+      enabled for a given platform. If the value is true, GINF
+      method which takes 3 parameters (u-id, bank-id and field-id)
+      will be used else GINF method with 2 parameters (field-id
+      and bank-id) will be used.
+
   "#gpio-cells":
     const: 2
 

dts/x86/intel/alder_lake.dtsi

@@ -57,83 +57,107 @@
 			acpi-hid = "INTC1057";
 			acpi-uid = "2";
 			group-index = <0x02>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_b: gpio_b {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x0>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_c: gpio_c {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x0B>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_d: gpio_d {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x8>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_e: gpio_e {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0xE>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_f: gpio_f {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0xC>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_h: gpio_h {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x7>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_i: gpio_i {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x9>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_s: gpio_s {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x6>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_r: gpio_r {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x3>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_t: gpio_t {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0x1>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 
 		gpio_v: gpio_v {
 			acpi-hid = "INTC1057";
 			acpi-uid = "0";
 			group-index = <0xA>;
+			int-stat-offset = <0x40>;
+			int-en-offset = <0x20>;
 			status = "okay";
 		};
 	};

dts/x86/intel/gpio_common.dtsi

@@ -145,6 +145,15 @@
 			status = "disabled";
 		};
 
+		gpio_v: gpio_v {
+			compatible = "intel,gpio";
+			interrupt-parent = <&intc>;
+			interrupts = <ACPI_IRQ_DETECT ACPI_IRQ_FLAG_DETECT 3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
 		vgpio: vgpio {
 			compatible = "intel,gpio";
 			interrupt-parent = <&intc>;

dts/x86/intel/panther_lake_h.dtsi

@@ -7,6 +7,8 @@
 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include "gpio_common.dtsi"
 
 / {
 	cpus {
@@ -49,6 +51,98 @@
 		#address-cells = <1>;
 	};
 
+	acpi {
+		gpio_a: gpio_a {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "3";
+			group-index = <0x02>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_b: gpio_b {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "5";
+			group-index = <0x00>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_c: gpio_c {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "0";
+			group-index = <0x01>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_d: gpio_d {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "5";
+			group-index = <0x01>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_e: gpio_e {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "1";
+			group-index = <0x01>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_f: gpio_f {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "1";
+			group-index = <0x00>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_h: gpio_h {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "3";
+			group-index = <0x01>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_s: gpio_s {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "4";
+			group-index = <0x00>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+
+		gpio_v: gpio_v {
+			acpi-hid = "INTC10BC";
+			acpi-uid = "0";
+			group-index = <0x00>;
+			acpi-ginf-3-param;
+			int-stat-offset = <0x30>;
+			int-en-offset = <0x20>;
+			status = "disabled";
+		};
+	};
+
 	pcie0: pcie0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -178,6 +272,7 @@
 			pw,cs-mode = <0>;
 			pw,cs-output = <0>;
 			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_e 17 GPIO_ACTIVE_LOW>;
 			clock-frequency = <100000000>;
 			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
 			interrupt-parent = <&intc>;
@@ -193,6 +288,7 @@
 			pw,cs-mode = <0>;
 			pw,cs-output = <0>;
 			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_f 17 GPIO_ACTIVE_LOW>;
 			clock-frequency = <100000000>;
 			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
 			interrupt-parent = <&intc>;
@@ -208,6 +304,7 @@
 			pw,cs-mode = <0>;
 			pw,cs-output = <0>;
 			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_f 18 GPIO_ACTIVE_LOW>;
 			clock-frequency = <100000000>;
 			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
 			interrupt-parent = <&intc>;

soc/intel/alder_lake/CMakeLists.txt

@@ -8,7 +8,7 @@ zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
 zephyr_cc_option(-march=goldmont)
 
 zephyr_library_sources(cpu.c)
-zephyr_library_sources(../common/soc_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO ../common/soc_gpio.c)
 
 zephyr_library_sources_ifdef(CONFIG_POWEROFF ../common/power.c)