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etienne-lms
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include: zephyr: dt-bindings: clock: use STM32 common clock source macros
Replace STM32_DOMAIN_CLOCK() and STM32_MCO_CFGR() macros in stm32 DT clock bindings header file with the common macro STM32_DT_CLOCK_SELECT(). By the way, add parentheses on argument where it mas missing. Signed-off-by: Etienne Carriere <[email protected]>
1 parent 3b8b266 commit 7113c06

24 files changed

+438
-435
lines changed

‎include/zephyr/dt-bindings/clock/stm32c0_clock.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -40,18 +40,18 @@
4040

4141
/** @brief Device domain clocks selection helpers */
4242
/** CCIPR devices */
43-
#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
44-
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
45-
#define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
46-
#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
43+
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
44+
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
45+
#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
46+
#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
4747
/** CSR1 devices */
48-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)
48+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG)
4949

5050
/** CFGR1 devices */
51-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
52-
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
53-
#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)
54-
#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)
51+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
52+
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
53+
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG)
54+
#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG)
5555

5656
/* MCO prescaler : division factor */
5757
#define MCO_PRE_DIV_1 0

‎include/zephyr/dt-bindings/clock/stm32f0_clock.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -39,17 +39,17 @@
3939

4040
/** @brief Device domain clocks selection helpers */
4141
/** CFGR3 devices */
42-
#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
43-
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
44-
#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
45-
#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG)
46-
#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
47-
#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
42+
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG)
43+
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG)
44+
#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG)
45+
#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CFGR3_REG)
46+
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG)
47+
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG)
4848
/** BDCR devices */
49-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
49+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
5050

5151
/** CFGR1 devices */
52-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
53-
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
52+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
53+
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
5454

5555
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32f10x_clock.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919

2020
/** CFGR1 devices */
2121
#undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity line devices. */
22-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
22+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
2323
/* No MCO prescaler support on STM32F1 series. */
2424

2525
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32f1_clock.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,13 +37,13 @@
3737

3838
/** @brief Device domain clocks selection helpers */
3939
/** CFGR2 devices */
40-
#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG)
41-
#define I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG)
40+
#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 17, CFGR2_REG)
41+
#define I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CFGR2_REG)
4242
/** BDCR devices */
43-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
43+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
4444

4545
/** CFGR1 devices */
46-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
46+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
4747
/* No MCO prescaler support on STM32F1 series. */
4848

4949
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32f3_clock.h‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -40,27 +40,27 @@
4040

4141
/** @brief Device domain clocks selection helpers) */
4242
/** CFGR devices */
43-
#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
44-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
45-
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)
43+
#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
44+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
45+
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG)
4646
/** CFGR3 devices */
47-
#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
48-
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
49-
#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)
50-
#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
51-
#define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)
52-
#define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)
53-
#define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)
54-
#define TIM16_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)
55-
#define TIM17_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)
56-
#define TIM20_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG)
57-
#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
58-
#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
59-
#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG)
60-
#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG)
61-
#define TIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG)
62-
#define TIM3_4_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG)
47+
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG)
48+
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG)
49+
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 5, CFGR3_REG)
50+
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG)
51+
#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CFGR3_REG)
52+
#define TIM8_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 9, CFGR3_REG)
53+
#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CFGR3_REG)
54+
#define TIM16_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CFGR3_REG)
55+
#define TIM17_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR3_REG)
56+
#define TIM20_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CFGR3_REG)
57+
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG)
58+
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG)
59+
#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CFGR3_REG)
60+
#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR3_REG)
61+
#define TIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CFGR3_REG)
62+
#define TIM3_4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 25, CFGR3_REG)
6363
/** BDCR devices */
64-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
64+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
6565

6666
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32f410_clock.h‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -14,19 +14,19 @@
1414

1515
/** @brief Device domain clocks selection helpers */
1616
/** DCKCFGR devices */
17-
#define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
18-
#define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
19-
#define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
20-
#define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
21-
#define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG)
22-
#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG)
23-
#define CKDFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG)
17+
#define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG)
18+
#define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG)
19+
#define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG)
20+
#define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG)
21+
#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 25, DCKCFGR_REG)
22+
#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 27, DCKCFGR_REG)
23+
#define CKDFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, DCKCFGR_REG)
2424

2525
/** DCKCFGR2 devices */
26-
#define I2CFMP1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
27-
#define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
28-
#define SDIO_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
29-
#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG)
26+
#define I2CFMP1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG)
27+
#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG)
28+
#define SDIO_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG)
29+
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, DCKCFGR2_REG)
3030

3131
/* F4 generic I2S_SEL is not compatible with F410 devices */
3232
#ifdef I2S_SEL

‎include/zephyr/dt-bindings/clock/stm32f427_clock.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@
1313

1414
/** @brief Device domain clocks selection helpers */
1515
/** DCKCFGR devices */
16-
#define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
17-
#define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
18-
#define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
19-
#define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
20-
#define CLK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG)
21-
#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG)
22-
#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG)
16+
#define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG)
17+
#define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG)
18+
#define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG)
19+
#define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG)
20+
#define CLK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR_REG)
21+
#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR_REG)
22+
#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR_REG)
2323

2424
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32f4_clock.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,13 +50,13 @@
5050

5151
/** @brief Device domain clocks selection helpers */
5252
/** CFGR devices */
53-
#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
54-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
55-
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
56-
#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
57-
#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
53+
#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
54+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)
55+
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
56+
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)
57+
#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)
5858
/** BDCR devices */
59-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
59+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
6060

6161
/* MCO prescaler : division factor */
6262
#define MCO_PRE_DIV_1 0

‎include/zephyr/dt-bindings/clock/stm32f7_clock.h‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -48,11 +48,11 @@
4848

4949
/** @brief Device domain clocks selection helpers */
5050
/** CFGR devices */
51-
#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
52-
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
53-
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
54-
#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
55-
#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
51+
#define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
52+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)
53+
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
54+
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)
55+
#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)
5656

5757
/* MCO prescaler : division factor */
5858
#define MCO_PRE_DIV_1 0
@@ -62,31 +62,31 @@
6262
#define MCO_PRE_DIV_5 7
6363

6464
/** BDCR devices */
65-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
65+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
6666

6767
/** @brief RCC_DKCFGR register offset */
6868
#define DCKCFGR1_REG 0x8C
6969
#define DCKCFGR2_REG 0x90
7070

7171
/** @brief Dedicated clocks configuration register selection helpers */
7272
/** DKCFGR2 devices */
73-
#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)
74-
#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)
75-
#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)
76-
#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)
77-
#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)
78-
#define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)
79-
#define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)
80-
#define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG)
81-
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG)
82-
#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG)
83-
#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG)
84-
#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
85-
#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG)
86-
#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG)
87-
#define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
88-
#define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
89-
#define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG)
90-
#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG)
73+
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, DCKCFGR2_REG)
74+
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, DCKCFGR2_REG)
75+
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, DCKCFGR2_REG)
76+
#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, DCKCFGR2_REG)
77+
#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, DCKCFGR2_REG)
78+
#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, DCKCFGR2_REG)
79+
#define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, DCKCFGR2_REG)
80+
#define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, DCKCFGR2_REG)
81+
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, DCKCFGR2_REG)
82+
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, DCKCFGR2_REG)
83+
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR2_REG)
84+
#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG)
85+
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, DCKCFGR2_REG)
86+
#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 26, DCKCFGR2_REG)
87+
#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG)
88+
#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG)
89+
#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR2_REG)
90+
#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 30, DCKCFGR2_REG)
9191

9292
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32g0_clock.h‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -44,26 +44,26 @@
4444

4545
/** @brief Device domain clocks selection helpers */
4646
/** CCIPR devices */
47-
#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
48-
#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
49-
#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
50-
#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG)
51-
#define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
52-
#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
53-
#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
54-
#define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
55-
#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
56-
#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
57-
#define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CCIPR_REG)
58-
#define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG)
59-
#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
60-
#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
47+
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
48+
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
49+
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
50+
#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG)
51+
#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
52+
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
53+
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
54+
#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
55+
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
56+
#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
57+
#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG)
58+
#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
59+
#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
60+
#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
6161
/** CCIPR2 devices */
62-
#define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
63-
#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR2_REG)
64-
#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR2_REG)
65-
#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
62+
#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
63+
#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
64+
#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
65+
#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
6666
/** BDCR devices */
67-
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
67+
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
6868

6969
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */

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