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soc: renesas: ra: Add initial support for RA8M1 SOC series
Add minimal support for RA8M1 SOC series. Signed-off-by: Duy Nguyen <[email protected]> Signed-off-by: Quy Tran <[email protected]>
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‎dts/arm/renesas/ra/ra8/r7fa8m1ahecbd.dtsi

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra8/r7fa8m1xh.dtsi>

‎dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra8/ra8x1.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra8-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra8-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra8-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_2>;
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mul = <96 0>;
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divp = <RA_PLL_DIV_2>;
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freqp = <DT_FREQ_M(480)>;
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divq = <RA_PLL_DIV_2>;
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freqq = <DT_FREQ_M(480)>;
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divr = <RA_PLL_DIV_2>;
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freqr = <DT_FREQ_M(480)>;
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status = "disabled";
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};
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pll2: pll2 {
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compatible = "renesas,ra8-cgc-pll";
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#clock-cells = <0>;
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/* PLL2 */
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source = <RA_PLL_SOURCE_DISABLE>;
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div = <RA_PLL_DIV_2>;
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mul = <96 0>;
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divp = <RA_PLL_DIV_2>;
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freqp = <DT_FREQ_M(0)>;
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divq = <RA_PLL_DIV_2>;
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freqq = <DT_FREQ_M(0)>;
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divr = <RA_PLL_DIV_2>;
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freqr = <DT_FREQ_M(0)>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra8-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
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status = "okay";
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cpuclk: cpuclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <0>;
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status = "okay";
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};
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iclk: iclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <0>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <0>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_8>;
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#clock-cells = <0>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_8>;
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#clock-cells = <0>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <0>;
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status = "okay";
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};
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pclke: pclke {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <0>;
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status = "okay";
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};
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bclk: bclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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bclkout: bclkout {
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compatible = "renesas,ra8-cgc-busclk";
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clk_out_div = <2>;
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sdclk = <1>;
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#clock-cells = <0>;
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};
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#clock-cells = <0>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_8>;
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#clock-cells = <0>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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sciclk: sciclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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spiclk: spiclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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canfdclk: canfdclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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i3cclk: i3cclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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u60clk: u60clk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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octaspiclk: octaspiclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <0>;
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status = "disabled";
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra8/ra8x1.dtsi

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8.1-m.dtsi>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m85";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8.1m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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sram0: memory@22000000 {
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compatible = "mmio-sram";
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reg = <0x22000000 DT_SIZE_K(896)>;
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};
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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option_setting_ofs: option_setting_ofs@300a100 {
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compatible = "zephyr,memory-region";
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reg = <0x0300a100 0x18>;
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zephyr,memory-region = "OPTION_SETTING_OFS";
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status = "okay";
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};
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option_setting_sas: option_setting_sas@300a134 {
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compatible = "zephyr,memory-region";
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reg = <0x0300a134 0xcc>;
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zephyr,memory-region = "OPTION_SETTING_SAS";
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status = "okay";
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};
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option_setting_s: option_setting_s@300a200 {
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compatible = "zephyr,memory-region";
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reg = <0x0300a200 0x100>;
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zephyr,memory-region = "OPTION_SETTING_S";
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};

‎dts/bindings/clock/renesas,ra8-cgc-busclk.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA8 External Bus Clock
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compatible: "renesas,ra8-cgc-busclk"
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include: [clock-controller.yaml, base.yaml]
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properties:
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clk_out_div:
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type: int
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enum:
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- 0
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- 1
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- 2
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description: |
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Select EBCLK division ratio from BCLK
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- 0: disable
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- 1: EBCLK div/1
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- 2: EBCLK div/2
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sdclk:
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type: int
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enum:
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- 0
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- 1
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description: |
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SDCLK enable or disable
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- 0: disable
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- 1: enable

‎dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA8 Clock Generation Circuit external clock configuration
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compatible: "renesas,ra8-cgc-external-clock"
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include: [fixed-clock.yaml, base.yaml]
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properties:
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mosel:
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type: int
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default: 0
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enum:
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- 0
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- 1
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description: |
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Choose the way for external Clock Oscillator supply
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0: Resonator
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1: External clock input

‎dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA8 clock control node pclk block
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compatible: "renesas,ra8-cgc-pclk-block"
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include: [clock-controller.yaml, base.yaml]
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properties:
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sysclock-src:
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required: true
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type: int

‎dts/bindings/clock/renesas,ra8-cgc-pclk.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA8 Clock Control Peripheral Clock
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compatible: "renesas,ra8-cgc-pclk"
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include: [clock-controller.yaml, base.yaml]
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properties:
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clk_src:
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type: int
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clk_div:
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type: int
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required: true
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description: Prescale divider to calculate the subclock frequency from the
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system clock frequency.
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"#clock-cells":
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const: 0

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