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samples/tests: adc: enable samples/tests for s32z270
enable samples/tests adc for s32z270 Signed-off-by: Ha Duong Quang <[email protected]>
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‎samples/drivers/adc/adc_dt/boards/s32z2xxdc2_s32z270_rtu0.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/adc/adc.h>
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/ {
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zephyr,user {
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io-channels = <&sar_adc0 2>, <&sar_adc0 3>, <&sar_adc0 4>, <&sar_adc0 5>,
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<&sar_adc1 3>, <&sar_adc1 4>, <&sar_adc1 5>, <&sar_adc1 6>;
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};
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};
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&sar_adc0 {
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group-channel = "precision";
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callback-select = "normal-end-chain";
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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vref-mv = <1800>;
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channel@2 {
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reg = <2>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@5 {
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reg = <5>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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};
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&sar_adc1 {
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group-channel = "standard";
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@5 {
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reg = <5>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@6 {
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reg = <6>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/s32z2xxdc2_s32z270_rtu1.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "s32z2xxdc2_s32z270_rtu0.overlay"

‎samples/drivers/adc/adc_sequence/boards/s32z2xxdc2_s32z270_rtu0.conf‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SEQUENCE_RESOLUTION=12

‎samples/drivers/adc/adc_sequence/boards/s32z2xxdc2_s32z270_rtu0.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/adc/adc.h>
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/ {
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aliases {
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adc0 = &sar_adc0;
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};
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zephyr,user {
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io-channels = <&sar_adc0 3>, <&sar_adc0 4>, <&sar_adc0 5>, <&sar_adc0 6>;
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};
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};
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&sar_adc0 {
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group-channel = "standard";
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@4 {
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reg = <4>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@5 {
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reg = <5>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@6 {
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reg = <6>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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};

‎samples/drivers/adc/adc_sequence/boards/s32z2xxdc2_s32z270_rtu1.conf‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SEQUENCE_RESOLUTION=12

‎samples/drivers/adc/adc_sequence/boards/s32z2xxdc2_s32z270_rtu1.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "s32z2xxdc2_s32z270_rtu0.overlay"

‎tests/drivers/adc/adc_api/boards/s32z2xxdc2_s32z270_rtu0.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/adc/adc.h>
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/ {
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zephyr,user {
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io-channels = <&sar_adc0 2>, <&sar_adc0 3>;
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};
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};
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&sar_adc0 {
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group-channel = "precision";
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@2 {
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reg = <2>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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channel@3 {
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reg = <3>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <12>;
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};
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};

‎tests/drivers/adc/adc_api/boards/s32z2xxdc2_s32z270_rtu1.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "s32z2xxdc2_s32z270_rtu0.overlay"

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