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Board: amd : add board support for the Audio DSP on ACP_6_0 soc.
Create a acp_6_0_adsp board support for the Audio DSP on ACP soc. Signed-off-by: DineshKumar Kalva <[email protected]>
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‎soc/amd/acp_6_0/adsp/CMakeLists.txt‎ renamed to ‎boards/amd/acp_6_0_adsp/Kconfig.acp_6_0_adsp‎

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# Copyright (c) 2024 AMD
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(include)
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config BOARD_ACP_6_0_ADSP
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select SOC_ACP_6_0

‎boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts‎

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/*
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* Copyright (c) 2024 AMD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <amd/acp_6_0.dtsi>
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/ {
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model = "AMD ACP_6_0 Audio DSP";
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compatible = "acp_6_0";
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};

‎boards/amd/acp_6_0_adsp/acp_6_0_adsp.yml‎

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#
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# Copyright 2024 AMD
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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identifier: acp_6_0_adsp/acp_6_0
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name: AMD ACP6.0 Audio DSP
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type: mcu
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arch: xtensa
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toolchain:
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- zephyr
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- xcc
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vendor: amd

‎boards/amd/acp_6_0_adsp/acp_6_0_adsp_defconfig‎

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=y
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CONFIG_XTENSA_RESET_VECTOR=y
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CONFIG_OUTPUT_SYMBOLS=y
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CONFIG_MULTI_LEVEL_INTERRUPTS=n
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CONFIG_2ND_LEVEL_INTERRUPTS=n
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CONFIG_DCACHE_LINE_SIZE_DETECT=n
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CONFIG_DCACHE_LINE_SIZE=128

‎boards/amd/acp_6_0_adsp/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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board_set_flasher_ifnset(misc-flasher)
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board_finalize_runner_args(misc-flasher)
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board_set_rimage_target(rmb)

‎boards/amd/acp_6_0_adsp/board.yml‎

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board:
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name: acp_6_0_adsp
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full_name: ACP 6.0 Xtensa Audio DSP
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vendor: amd
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socs:
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- name: acp_6_0

‎boards/amd/acp_6_0_adsp/doc/index.rst‎

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.. zephyr:board:: acp_6_0_adsp
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Overview
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********
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ACP 6.0 is Audio co-processor in AMD SoC based on HiFi5 DSP Xtensa Architecture,
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Zephyr OS is ported to run various audio and speech use cases on
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the SOF based framework.
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SOF can be built with either Zephyr or Cadence's proprietary
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Xtensa OS (XTOS) and run on a ACP 6.0 AMD platforms.
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Hardware
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********
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- Board features:
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- RAM: 1.75MB HP SRAM & 512KB configurable IRAM/DRAM
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- Audio Interfaces:
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- 1 x SP (I2S, PCM),
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- 1 x BT (I2S, PCM),
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- 1 x HS (I2S, PCM),
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- DMIC
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Supported Features
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==================
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The following hardware features are supported:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| I2S | on-chip | I2S controller |
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+-----------+------------+-------------------------------------+
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| DMIC(PDM) | on-chip | PDM controller |
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+-----------+------------+-------------------------------------+
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System Clock
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============
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The ACP 6.0 SoC operates with an audio clock frequency ranging from 200 to 800 MHz.
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System requirements
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*******************
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Xtensa Toolchain (optional)
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===========================
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The Zephyr SDK provides GCC-based toolchains necessary to build Zephyr for
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the AMD ACP boards. For users looking for higher optimization levels,
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building with the proprietary Xtensa toolchain from Cadence
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might be preferable.
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The following instructions assume you have purchased and
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installed the toolchain(s) and core(s) for your board following
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instructions from Xtensa documentation.
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If you choose to build with the Xtensa toolchain instead of the Zephyr SDK, set
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the following environment variables specific to the board in addition to the
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Xtensa toolchain environment variable listed below.
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First, make sure, the necessary license is available from
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Cadence and set the license variables as per the instruction from Cadence.
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Next, set the following environment variables:
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The bottom three variables are specific to acp_6_0.
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.. code-block:: shell
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export XTENSA_TOOLCHAIN_PATH="tools installed path"
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export XTENSA_BUILDS_DIR="user build directory path"
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export ZEPHYR_TOOLCHAIN_VARIANT=xcc
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export TOOLCHAIN_VER=RI-2019.1-linux
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export XTENSA_CORE=LX7_HiFi5_PROD
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Programming and Debugging
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*************************
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Building
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========
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Build as usual.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: acp_6_0_adsp/acp_6_0
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:goals: build
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Flashing
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========
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AMD supports only signed images flashing on ACP 6.0 platforms
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through ACP Linux Driver.
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The following boot sequence messages can be observed in dmesg
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- booting DSP firmware
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- ACP_DSP0_RUNSTALL : 0x0
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- ipc rx: 0x70000000
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- Firmware info: version 2:11:99-03a9d
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- Firmware: ABI 3:29:1 Kernel ABI 3:23:0
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- mailbox upstream 0x0 - size 0x400
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- mailbox downstream 0x400 - size 0x400
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- stream region 0x1000 - size 0x400
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- debug region 0x800 - size 0x400
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- fw_state change: 3 -> 6
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- ipc rx done: 0x70000000
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- firmware boot complete

‎soc/amd/acp_6_0/CMakeLists.txt‎

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if(CONFIG_SOC_ACP_6_0)
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zephyr_include_directories(adsp)
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add_subdirectory(adsp)
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# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
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add_custom_target(zephyr.ri ALL
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DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
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DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
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)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
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endif()

‎soc/amd/acp_6_0/Kconfig‎

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# SPDX-License-Identifier: Apache-2.0
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config SOC_ACP_6_0
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select XTENSA
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select XTENSA_GEN_HANDLERS
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select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
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select XTENSA_RESET_VECTOR
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select ATOMIC_OPERATIONS_BUILTIN

‎soc/amd/acp_6_0/Kconfig.defconfig‎

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if SOC_ACP_6_0
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config DCACHE_LINE_SIZE
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default 128
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default 128
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config CACHE_MANAGEMENT
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default n
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default n
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config XTENSA_TIMER
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default y
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default y
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 600000000 if XTENSA_TIMER
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config KERNEL_ENTRY
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default "__start"
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default 600000000 if XTENSA_TIMER
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config MULTI_LEVEL_INTERRUPTS
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default n
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default n
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config 2ND_LEVEL_INTERRUPTS
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default n
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default n
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config KERNEL_ENTRY
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default "__start"
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default "__start"
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endif

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