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drivers: video: ov2640 driver: Enhancing ov2640 driver
* Code formatting Signed-off-by: Roman Pustobaiev <[email protected]>
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‎drivers/video/ov2640.c‎

Lines changed: 113 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -151,88 +151,88 @@ LOG_MODULE_REGISTER(video_ov2640, CONFIG_VIDEO_LOG_LEVEL);
151151
#define REG32 0x32
152152
#define REG32_UXGA 0x36
153153

154-
#define CIF_WIDTH 352
155-
#define CIF_HEIGHT 288
156-
#define HD_720_WIDTH 1280
157-
#define HD_720_HEIGHT 720
158-
#define HD_1080_WIDTH 1920
159-
#define HD_1080_HEIGHT 1080
160-
#define QCIF_WIDTH 176
161-
#define QCIF_HEIGHT 144
162-
#define QQCIF_WIDTH 88
163-
#define QQCIF_HEIGHT 72
164-
#define QQVGA_WIDTH 160
165-
#define QQVGA_HEIGHT 120
166-
#define QVGA_WIDTH 320
167-
#define QVGA_HEIGHT 240
168-
#define SVGA_WIDTH 800
169-
#define SVGA_HEIGHT 600
170-
#define SXGA_WIDTH 1280
171-
#define SXGA_HEIGHT 1024
172-
#define VGA_WIDTH 640
173-
#define VGA_HEIGHT 480
174-
#define UXGA_WIDTH 1600
175-
#define UXGA_HEIGHT 1200
176-
#define XGA_WIDTH 1024
177-
#define XGA_HEIGHT 768
154+
#define CIF_WIDTH 352
155+
#define CIF_HEIGHT 288
156+
#define HD_720_WIDTH 1280
157+
#define HD_720_HEIGHT 720
158+
#define HD_1080_WIDTH 1920
159+
#define HD_1080_HEIGHT 1080
160+
#define QCIF_WIDTH 176
161+
#define QCIF_HEIGHT 144
162+
#define QQCIF_WIDTH 88
163+
#define QQCIF_HEIGHT 72
164+
#define QQVGA_WIDTH 160
165+
#define QQVGA_HEIGHT 120
166+
#define QVGA_WIDTH 320
167+
#define QVGA_HEIGHT 240
168+
#define SVGA_WIDTH 800
169+
#define SVGA_HEIGHT 600
170+
#define SXGA_WIDTH 1280
171+
#define SXGA_HEIGHT 1024
172+
#define VGA_WIDTH 640
173+
#define VGA_HEIGHT 480
174+
#define UXGA_WIDTH 1600
175+
#define UXGA_HEIGHT 1200
176+
#define XGA_WIDTH 1024
177+
#define XGA_HEIGHT 768
178178

179179
struct ov2640_reg {
180180
uint8_t addr;
181181
uint8_t value;
182182
};
183183

184184
struct ov2640_win_size {
185-
char *name;
186-
uint32_t width;
187-
uint32_t height;
188-
const struct ov2640_reg *regs;
189-
uint32_t regs_size;
185+
char *name;
186+
uint32_t width;
187+
uint32_t height;
188+
const struct ov2640_reg *regs;
189+
uint32_t regs_size;
190190
};
191191

192-
#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
193-
{ CTRLI, CTRLI_LP_DP | FIELD_PREP(GENMASK(5, 3), v_div) | \
194-
FIELD_PREP(GENMASK(2, 0), h_div)}, \
195-
{ ZMOW, FIELD_PREP(GENMASK(7, 0), (x) >> 2) }, \
196-
{ ZMOH, FIELD_PREP(GENMASK(7, 0), (y) >> 2) }, \
197-
{ ZMHH, FIELD_PREP(GENMASK(1, 0), (x) >> (8+2)) | FIELD_PREP(GENMASK(2, 2), (y) >> (8+2)) }, \
198-
{ R_DVP_SP, pclk_div }, \
199-
{ RESET, 0x00}
192+
#define OV2640_ZOOM_CONFIG(x, y, v_div, h_div, pclk_div) \
193+
{CTRLI, \
194+
CTRLI_LP_DP | FIELD_PREP(GENMASK(5, 3), v_div) | FIELD_PREP(GENMASK(2, 0), h_div)}, \
195+
{ZMOW, FIELD_PREP(GENMASK(7, 0), (x) >> 2)}, \
196+
{ZMOH, FIELD_PREP(GENMASK(7, 0), (y) >> 2)}, \
197+
{ZMHH, FIELD_PREP(GENMASK(1, 0), (x) >> (8 + 2)) | \
198+
FIELD_PREP(GENMASK(2, 2), (y) >> (8 + 2))}, \
199+
{R_DVP_SP, pclk_div}, {RESET, 0x00}
200200

201201
static const struct ov2640_reg ov2640_qqvga_regs[] = {
202-
PER_SIZE_REG_SEQ(QQVGA_WIDTH, QQVGA_HEIGHT, 3, 3, 8),
202+
OV2640_ZOOM_CONFIG(QQVGA_WIDTH, QQVGA_HEIGHT, 3, 3, 8),
203203
};
204204
static const struct ov2640_reg ov2640_qcif_regs[] = {
205-
PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
205+
OV2640_ZOOM_CONFIG(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
206206
};
207207
static const struct ov2640_reg ov2640_qvga_regs[] = {
208-
PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
208+
OV2640_ZOOM_CONFIG(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
209209
};
210210
static const struct ov2640_reg ov2640_cif_regs[] = {
211-
PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
211+
OV2640_ZOOM_CONFIG(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
212212
};
213213
static const struct ov2640_reg ov2640_vga_regs[] = {
214-
PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
214+
OV2640_ZOOM_CONFIG(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
215215
};
216216
static const struct ov2640_reg ov2640_svga_regs[] = {
217-
PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
217+
OV2640_ZOOM_CONFIG(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
218218
};
219219
static const struct ov2640_reg ov2640_xga_regs[] = {
220-
PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
221-
{ CTRLI, 0x00},
220+
OV2640_ZOOM_CONFIG(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
221+
{CTRLI, 0x00},
222222
};
223223
static const struct ov2640_reg ov2640_sxga_regs[] = {
224-
PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
225-
{ CTRLI, 0x00},
226-
{ R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
224+
OV2640_ZOOM_CONFIG(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
225+
{CTRLI, 0x00},
226+
{R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE},
227227
};
228228
static const struct ov2640_reg ov2640_uxga_regs[] = {
229-
PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
230-
{ CTRLI, 0x00},
231-
{ R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
229+
OV2640_ZOOM_CONFIG(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
230+
{CTRLI, 0x00},
231+
{R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE},
232232
};
233233

234-
#define OV2640_SIZE(n, w, h, r) \
235-
{.name = n, .width = w , .height = h, .regs = r, .regs_size = ARRAY_SIZE(r) }
234+
#define OV2640_SIZE(n, w, h, r) \
235+
{.name = n, .width = w, .height = h, .regs = r, .regs_size = ARRAY_SIZE(r)}
236236

237237
static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
238238
OV2640_SIZE("QQVGA", QQVGA_WIDTH, QQVGA_HEIGHT, ov2640_qqvga_regs),
@@ -429,60 +429,59 @@ static const struct ov2640_reg default_regs[] = {
429429
};
430430

431431
static const struct ov2640_reg uxga_regs[] = {
432-
{ BANK_SEL, BANK_SEL_SENSOR },
432+
{BANK_SEL, BANK_SEL_SENSOR},
433433
/* DSP input image resolution and window size control */
434-
{ COM7, COM7_RES_UXGA},
435-
{ COM1, 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
436-
{ REG32, REG32_UXGA }, /* UXGA=0x36, SVGA/CIF=0x09 */
437-
438-
{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIF=0x11 */
439-
{ HSTOP, 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
440-
441-
{ VSTART, 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
442-
{ VSTOP, 0x97 }, /* UXGA=0x97, SVGA/CIF=0x4b */
443-
{ 0x3d, 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
444-
445-
{ 0x35, 0x88 },
446-
{ 0x22, 0x0a },
447-
{ 0x37, 0x40 },
448-
{ 0x34, 0xa0 },
449-
{ 0x06, 0x02 },
450-
{ 0x0d, 0xb7 },
451-
{ 0x0e, 0x01 },
452-
{ 0x42, 0x83 },
434+
{COM7, COM7_RES_UXGA},
435+
{COM1, 0x0F}, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
436+
{REG32, REG32_UXGA}, /* UXGA=0x36, SVGA/CIF=0x09 */
437+
438+
{HSTART, 0x11}, /* UXGA=0x11, SVGA/CIF=0x11 */
439+
{HSTOP, 0x75}, /* UXGA=0x75, SVGA/CIF=0x43 */
440+
441+
{VSTART, 0x01}, /* UXGA=0x01, SVGA/CIF=0x00 */
442+
{VSTOP, 0x97}, /* UXGA=0x97, SVGA/CIF=0x4b */
443+
{0x3d, 0x34}, /* UXGA=0x34, SVGA/CIF=0x38 */
444+
445+
{0x35, 0x88},
446+
{0x22, 0x0a},
447+
{0x37, 0x40},
448+
{0x34, 0xa0},
449+
{0x06, 0x02},
450+
{0x0d, 0xb7},
451+
{0x0e, 0x01},
452+
{0x42, 0x83},
453453

454454
/*
455455
* Set DSP input image size and offset.
456456
* The sensor output image can be scaled with OUTW/OUTH
457457
*/
458-
{ BANK_SEL, BANK_SEL_DSP },
459-
{ R_BYPASS, R_BYPASS_DSP_BYPAS },
458+
{BANK_SEL, BANK_SEL_DSP},
459+
{R_BYPASS, R_BYPASS_DSP_BYPAS},
460460

461-
{ RESET, RESET_DVP },
462-
{ HSIZE8, (UXGA_WIDTH>>3)}, /* Image Horizontal Size HSIZE[10:3] */
463-
{ VSIZE8, (UXGA_HEIGHT>>3)}, /* Image Vertical Size VSIZE[10:3] */
461+
{RESET, RESET_DVP},
462+
{HSIZE8, (UXGA_WIDTH >> 3)}, /* Image Horizontal Size HSIZE[10:3] */
463+
{VSIZE8, (UXGA_HEIGHT >> 3)}, /* Image Vertical Size VSIZE[10:3] */
464464

465465
/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
466-
{ SIZEL, ((UXGA_WIDTH>>6)&0x40) | ((UXGA_WIDTH&0x7)<<3) | (UXGA_HEIGHT&0x7)},
466+
{SIZEL, ((UXGA_WIDTH >> 6) & 0x40) | ((UXGA_WIDTH & 0x7) << 3) | (UXGA_HEIGHT & 0x7)},
467467

468-
{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
469-
{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
470-
{ HSIZE, ((UXGA_WIDTH>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
471-
{ VSIZE, ((UXGA_HEIGHT>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
468+
{XOFFL, 0x00}, /* OFFSET_X[7:0] */
469+
{YOFFL, 0x00}, /* OFFSET_Y[7:0] */
470+
{HSIZE, ((UXGA_WIDTH >> 2) & 0xFF)}, /* H_SIZE[7:0] real/4 */
471+
{VSIZE, ((UXGA_HEIGHT >> 2) & 0xFF)}, /* V_SIZE[7:0] real/4 */
472472

473473
/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
474-
{ VHYX, ((UXGA_HEIGHT>>3)&0x80) | ((UXGA_WIDTH>>7)&0x08) },
475-
{ TEST, (UXGA_WIDTH>>4)&0x80}, /* H_SIZE[9] */
474+
{VHYX, ((UXGA_HEIGHT >> 3) & 0x80) | ((UXGA_WIDTH >> 7) & 0x08)},
475+
{TEST, (UXGA_WIDTH >> 4) & 0x80}, /* H_SIZE[9] */
476476

477-
{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
478-
CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
477+
{CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN},
479478

480479
/* H_DIVIDER/V_DIVIDER */
481-
{ CTRLI, CTRLI_LP_DP | 0x00},
480+
{CTRLI, CTRLI_LP_DP | 0x00},
482481
/* DVP prescaler */
483-
{ R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x04},
482+
{R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x04},
484483

485-
{ R_BYPASS, R_BYPASS_DSP_EN },
484+
{R_BYPASS, R_BYPASS_DSP_EN},
486485
/* Keep reset asserted as zoom config is coming next */
487486
/* { RESET, 0x00 }, */
488487
{0, 0},
@@ -556,24 +555,27 @@ struct ov2640_data {
556555
}
557556

558557
static const struct video_format_cap fmts[] = {
559-
OV2640_VIDEO_FORMAT_CAP(QQVGA_WIDTH, QQVGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 160 x 120 QQVGA */
560-
OV2640_VIDEO_FORMAT_CAP(QCIF_WIDTH, QCIF_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 176 x 144 QCIF */
561-
OV2640_VIDEO_FORMAT_CAP(CIF_WIDTH, CIF_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 352 x 288 CIF */
562-
OV2640_VIDEO_FORMAT_CAP(VGA_WIDTH, VGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 640 x 480 VGA */
563-
OV2640_VIDEO_FORMAT_CAP(SVGA_WIDTH, SVGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 800 x 600 SVGA */
564-
OV2640_VIDEO_FORMAT_CAP(XGA_WIDTH, XGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 1024 x 768 XVGA */
565-
OV2640_VIDEO_FORMAT_CAP(SXGA_WIDTH, SXGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 1280 x 1024 SXGA */
566-
OV2640_VIDEO_FORMAT_CAP(UXGA_WIDTH, UXGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 1600 x 1200 UXGA */
567-
OV2640_VIDEO_FORMAT_CAP(QQVGA_WIDTH, QQVGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 160 x 120 QQVGA */
568-
OV2640_VIDEO_FORMAT_CAP(QCIF_WIDTH, QCIF_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 176 x 144 QCIF */
569-
OV2640_VIDEO_FORMAT_CAP(CIF_WIDTH, CIF_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 352 x 288 CIF */
570-
OV2640_VIDEO_FORMAT_CAP(VGA_WIDTH, VGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 640 x 480 VGA */
571-
OV2640_VIDEO_FORMAT_CAP(SVGA_WIDTH, SVGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 800 x 600 SVGA */
572-
OV2640_VIDEO_FORMAT_CAP(XGA_WIDTH, XGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 1024 x 768 XVGA */
573-
OV2640_VIDEO_FORMAT_CAP(SXGA_WIDTH, SXGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 1280 x 1024 SXGA */
574-
OV2640_VIDEO_FORMAT_CAP(UXGA_WIDTH, UXGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 1600 x 1200 UXGA */
575-
{ 0 }
576-
};
558+
OV2640_VIDEO_FORMAT_CAP(QQVGA_WIDTH, QQVGA_HEIGHT,
559+
VIDEO_PIX_FMT_RGB565), /* 160 x 120 QQVGA */
560+
OV2640_VIDEO_FORMAT_CAP(QCIF_WIDTH, QCIF_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 176 x 144 QCIF */
561+
OV2640_VIDEO_FORMAT_CAP(CIF_WIDTH, CIF_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 352 x 288 CIF */
562+
OV2640_VIDEO_FORMAT_CAP(VGA_WIDTH, VGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 640 x 480 VGA */
563+
OV2640_VIDEO_FORMAT_CAP(SVGA_WIDTH, SVGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 800 x 600 SVGA */
564+
OV2640_VIDEO_FORMAT_CAP(XGA_WIDTH, XGA_HEIGHT, VIDEO_PIX_FMT_RGB565), /* 1024 x 768 XVGA */
565+
OV2640_VIDEO_FORMAT_CAP(SXGA_WIDTH, SXGA_HEIGHT,
566+
VIDEO_PIX_FMT_RGB565), /* 1280 x 1024 SXGA */
567+
OV2640_VIDEO_FORMAT_CAP(UXGA_WIDTH, UXGA_HEIGHT,
568+
VIDEO_PIX_FMT_RGB565), /* 1600 x 1200 UXGA */
569+
OV2640_VIDEO_FORMAT_CAP(QQVGA_WIDTH, QQVGA_HEIGHT,
570+
VIDEO_PIX_FMT_JPEG), /* 160 x 120 QQVGA */
571+
OV2640_VIDEO_FORMAT_CAP(QCIF_WIDTH, QCIF_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 176 x 144 QCIF */
572+
OV2640_VIDEO_FORMAT_CAP(CIF_WIDTH, CIF_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 352 x 288 CIF */
573+
OV2640_VIDEO_FORMAT_CAP(VGA_WIDTH, VGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 640 x 480 VGA */
574+
OV2640_VIDEO_FORMAT_CAP(SVGA_WIDTH, SVGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 800 x 600 SVGA */
575+
OV2640_VIDEO_FORMAT_CAP(XGA_WIDTH, XGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 1024 x 768 XVGA */
576+
OV2640_VIDEO_FORMAT_CAP(SXGA_WIDTH, SXGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 1280 x 1024 SXGA */
577+
OV2640_VIDEO_FORMAT_CAP(UXGA_WIDTH, UXGA_HEIGHT, VIDEO_PIX_FMT_JPEG), /* 1600 x 1200 UXGA */
578+
{0}};
577579

578580
static int ov2640_write_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr,
579581
uint8_t value)
@@ -858,9 +860,10 @@ static const struct ov2640_win_size *ov2640_select_win(uint32_t width, uint32_t
858860
{
859861
int i;
860862
for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
861-
if (ov2640_supported_win_sizes[i].width >= width &&
862-
ov2640_supported_win_sizes[i].height >= height)
863+
if (ov2640_supported_win_sizes[i].width >= width &&
864+
ov2640_supported_win_sizes[i].height >= height) {
863865
return &ov2640_supported_win_sizes[i];
866+
}
864867
}
865868
return NULL;
866869
}

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