boards: openhwgroup: add CV64A6 Testbench

Adds support for the CVA6 CPU in the hardware simulation / testbench
environment. Especially, configurations are added that allow the
application to indicate success or error to the testbench.
The SoC currently contains the CVA6 CPU in 64-bit configuration with the
SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for
booting from SD, a boot ROM, and I2C controller for on-board audio, a
GPIO and the lowRISC ethernet subsystem (which is currently without a
driver in zephyr).
Two sample applications are provided, demonstrating how to indicate
success or failure to the testbench.

Signed-off-by: Eric Ackermann <[email protected]>

Author: WorldofJARcraft

boards/openhwgroup/cv64a6_testbench/Kconfig.cv64a6_testbench

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV64A6_TESTBENCH
+	select SOC_CV64A6
+	select SOC_SERIES_CV64A6_PROVIDE_TEST_POWEROFF

boards/openhwgroup/cv64a6_testbench/board.yml

@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv64a6_testbench
+  vendor: openhwgroup
+  socs:
+    - name: cv64a6

boards/openhwgroup/cv64a6_testbench/cv64a6_testbench.dts

@@ -0,0 +1,45 @@
+/*
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv64a6.dtsi>
+
+/ {
+	model = "CVA6 CPU in testbench";
+	compatible = "ariane,cv64a6_testbench";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&clint{
+	status = "okay";
+};
+
+
+&dma0 {
+	status = "disabled";
+};
+
+
+
+&mdio0{
+	status = "disabled";
+};
+
+&eth0 {
+	status = "disabled";
+};

boards/openhwgroup/cv64a6_testbench/cv64a6_testbench_defconfig

@@ -0,0 +1,44 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
+CONFIG_FPU=y
+CONFIG_POWEROFF=y
+
+# RNG
+CONFIG_TIMER_RANDOM_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+
+# IRQs
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+# 1 PLIC
+CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
+CONFIG_1ST_LEVEL_INTERRUPT_BITS=7
+CONFIG_2ND_LEVEL_INTERRUPT_BITS=23
+CONFIG_PLIC=y
+CONFIG_3RD_LEVEL_INTERRUPTS=n
+CONFIG_3RD_LEVEL_INTERRUPT_BITS=0
+
+
+# logging
+CONFIG_LOG=y
+# immediate is required so it is not lost on test failure
+CONFIG_LOG_MODE_IMMEDIATE=y
+CONFIG_LOG_DEFAULT_LEVEL=4
+CONFIG_THREAD_NAME=y
+
+CONFIG_ISR_STACK_SIZE=32768
+CONFIG_MAIN_STACK_SIZE=32768
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=32768
+CONFIG_IDLE_STACK_SIZE=32768
+CONFIG_NET_TCP_WORKQ_STACK_SIZE=32768

samples/boards/openhwgroup/sim_fail/CMakeLists.txt

@@ -0,0 +1,9 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(cv64a6_sim_fail)
+
+target_sources(app PRIVATE src/main.c)

samples/boards/openhwgroup/sim_fail/README.rst

@@ -0,0 +1,32 @@
+.. _hello_world:
+
+Failing test
+###########
+
+Overview
+********
+
+A simple sample that can be used in the cv64a6 simulator.
+Prints "Test failure" to the console and indicates failure to the testbench.
+
+Building and Running
+********************
+
+This application can be built and executed in the cv64a6 testbench as follows:
+
+.. code-block:: console
+   west build -p always -b cv64a6_testbench samples/boards/openhwgroup/cv64a6/sim_fail/
+   ln -s $(pwd)/build/zephyr/zephyr.elf build/zephyr/zephyr.o
+   python3 $CVA6_ROOT/verif/sim/cva6.py --elf_tests $ZEPHYR_ROOT/build/zephyr/zephyr.o  --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=veri-testharness --spike_params="/top/max_steps_enabled=y" $DV_OPTSreset
+
+
+To build for another board, change "cv64a6_testbench" above to that board's name.
+
+Sample Output
+=============
+
+.. code-block:: console
+
+    Test Failure x86
+
+Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.

samples/boards/openhwgroup/sim_fail/prj.conf

@@ -0,0 +1 @@
+# nothing here

samples/boards/openhwgroup/sim_fail/sample.yaml

@@ -0,0 +1,17 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+sample:
+  description: Test failure sample adapted for CVA6 testbench
+  name: Test failure test
+common:
+  tags: introduction
+  integration_platforms:
+    - native_sim
+  harness: console
+  harness_config:
+    type: one_line
+    regex:
+      - "Test Failure (.*)"
+tests:
+  sample.basic.helloworld:
+    tags: introduction

samples/boards/openhwgroup/sim_fail/src/main.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX - License - Identifier : Apache-2.0
+ */
+#include <cv64a6.h>
+#include <stdio.h>
+
+
+int main(void)
+{
+	printf("Test failure %s\n", CONFIG_BOARD_TARGET);
+
+	z_cv64a6_finish_test(0xdead);
+
+	return 0;
+}

samples/boards/openhwgroup/sim_hello_world/CMakeLists.txt

@@ -0,0 +1,9 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(hello_world_cv64a6_sim)
+
+target_sources(app PRIVATE src/main.c)