drivers: video Add Restructure of set_fmt function

drivers: video Add Restructure of set_fmt function

set_fmt split to 0v7670_set_fmt & 0v7675_set_fmt.
Added separate RGB565 settings for cameras based on OpenMv

Signed-off-by: Mike S <[email protected]>

Author: mjs513

drivers/video/ov767x.c

@@ -1,6 +1,8 @@
 /*
  * Copyright 2024 NXP
  * Copyright 2021 Arduino SA
+ * Copyright (c) 2013-2021 Ibrahim Abdelkader <[email protected]>
+ * Copyright (c) 2013-2021 Kwabena W. Agyeman <[email protected]>
  * Copyright (c) 2025 Michael Smorto
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -134,15 +136,16 @@ struct ov767x_data {
 #define OV7670_HAECC5             0xA8
 #define OV7670_HAECC6             0xA9
 
-/* Addition defines for OV7675 */
-#define OV7675_RGB444           0x8C /* REG444 */
-#define OV7675_COM3_DCW_EN      0x04 /* DCW enable */
-#define OV7670_COM1             0x04 /*Com Cntrl1 */
-#define OV7675_COM7_RGB_FMT     0x04 /* Output format RGB        */
-#define OV7675_COM13_GAMMA_EN   0x80 /* Gamma enable */
-#define OV7675_COM13_UVSAT_AUTO 0x40 /* UV saturation level - UV auto adjustment. */
-#define OV7675_COM15_OUT_00_FF  0xC0 /* Output data range 00 to FF  */
-#define OV7675_COM15_FMT_RGB565 0x10 /* Normal RGB 565 output       */
+/* Addition defines to support OV7675 */
+#define OV7670_RGB444               0x8C /* REG444 */
+#define OV7675_COM3_DCW_EN          0x04 /* DCW enable */
+#define OV7670_COM1                 0x04 /*Com Cntrl1 */
+#define OV7675_COM7_RGB_FMT         0x04 /* Output format RGB        */
+#define OV7675_COM13_GAMMA_EN       0x80 /* Gamma enable */
+#define OV7675_COM13_UVSAT_AUTO     0x40 /* UV saturation level - UV auto adjustment. */
+#define OV7675_COM15_OUT_00_FF      0xC0 /* Output data range 00 to FF  */
+#define OV7675_COM15_FMT_RGB_NORMAL 0x00 /* Normal RGB normal output    */
+#define OV7675_COM15_FMT_RGB565     0x10 /* Normal RGB 565 output       */
 
 /* OV7670 definitions */
 #define OV7670_PROD_ID 0x76
@@ -342,25 +345,10 @@ static const struct video_reg8 ov767x_init_regtbl[] = {
 	{0xb8, 0x0a},
 };
 
-static const struct video_reg8 ov767x_rgb565_regs[] = {
-	{OV7670_COM7, OV7675_COM7_RGB_FMT}, /* Selects RGB mode */
-	{OV7675_RGB444, 0x00},              /* No RGB444 please */
-	{OV7670_COM1, 0x00},                /* CCIR601 */
-	{OV7670_COM15, OV7675_COM15_OUT_00_FF | OV7675_COM15_FMT_RGB565},
-	{OV7670_COM9, 0x38}, /* 16x gain ceiling; 0x8 is reserved bit */
-	{0x4f, 0xb3},        /* "matrix coefficient 1" */
-	{0x50, 0xb3},        /* "matrix coefficient 2" */
-	{0x51, 0x00},        /* "matrix Coefficient 3" */
-	{0x52, 0x3d},        /* "matrix coefficient 4" */
-	{0x53, 0xa7},        /* "matrix coefficient 5" */
-	{0x54, 0xe4},        /* "matrix coefficient 6" */
-	{OV7670_COM13, OV7675_COM13_GAMMA_EN | OV7675_COM13_UVSAT_AUTO},
-};
-
 /* TODO: These registers probably need to be fixed too. */
 static const struct video_reg8 ov767x_yuv422_regs[] = {
 	{OV7670_COM7, 0x00},   /* Selects YUV mode */
-	{OV7675_RGB444, 0x00}, /* No RGB444 please */
+	{OV7670_RGB444, 0x00}, /* No RGB444 please */
 	{OV7670_COM1, 0x00},   /* CCIR601 */
 	{OV7670_COM15, OV7675_COM15_OUT_00_FF},
 	{OV7670_COM9, 0x48}, /* 32x gain ceiling; 0x8 is reserved bit */
@@ -373,6 +361,22 @@ static const struct video_reg8 ov767x_yuv422_regs[] = {
 	{OV7670_COM13, OV7675_COM13_GAMMA_EN | OV7675_COM13_UVSAT_AUTO},
 };
 
+#if DT_HAS_COMPAT_STATUS_OKAY(ovti_ov7670)
+static const struct video_reg8 ov7670_rgb565_regs[] = {
+	{OV7670_COM7, OV7675_COM7_RGB_FMT}, /* Selects RGB mode */
+	{OV7670_RGB444, 0x00},              /* No RGB444 please */
+	{OV7670_COM1, 0x00},                /* CCIR601 */
+	{OV7670_COM15, OV7675_COM15_OUT_00_FF | OV7675_COM15_FMT_RGB565},
+	{OV7670_COM9, 0x6a}, /* 16x gain ceiling; 0x8 is reserved bit */
+	{0x4f, 0xb3},        /* "matrix coefficient 1" */
+	{0x50, 0xb3},        /* "matrix coefficient 2" */
+	{0x51, 0x00},        /* "matrix Coefficient 3" */
+	{0x52, 0x3d},        /* "matrix coefficient 4" */
+	{0x53, 0xa7},        /* "matrix coefficient 5" */
+	{0x54, 0xe4},        /* "matrix coefficient 6" */
+	{OV7670_COM13, OV7675_COM13_UVSAT_AUTO},
+};
+
 /* Resolution settings for camera, based on those present in MCUX SDK */
 static const struct video_reg8 ov7670_regs_qcif[] = {
 	{OV7670_COM7, 0x2c},
@@ -417,6 +421,23 @@ static const struct video_reg8 ov7670_regs_vga[] = {
 	{OV7670_SCALING_PCLK_DIV, 0xf0},
 	{OV7670_SCALING_PCLK_DELAY, 0x02},
 };
+#endif
+
+#if DT_HAS_COMPAT_STATUS_OKAY(ovti_ov7675)
+static const struct video_reg8 ov7675_rgb565_regs[] = {
+	{OV7670_COM7, OV7675_COM7_RGB_FMT}, /* Selects RGB mode */
+	{OV7670_RGB444, 0x00},              /* No RGB444 please */
+	{OV7670_COM1, 0x00},                /* CCIR601 */
+	{OV7670_COM15, OV7675_COM15_OUT_00_FF | OV7675_COM15_FMT_RGB565},
+	{OV7670_COM9, 0x38}, /* 16x gain ceiling; 0x8 is reserved bit */
+	{0x4f, 0xb3},        /* "matrix coefficient 1" */
+	{0x50, 0xb3},        /* "matrix coefficient 2" */
+	{0x51, 0x00},        /* "matrix Coefficient 3" */
+	{0x52, 0x3d},        /* "matrix coefficient 4" */
+	{0x53, 0xa7},        /* "matrix coefficient 5" */
+	{0x54, 0xe4},        /* "matrix coefficient 6" */
+	{OV7670_COM13, OV7675_COM13_GAMMA_EN | OV7675_COM13_UVSAT_AUTO},
+};
 
 static const struct video_reg8 ov7675_regs_vga[] = {
 	{OV7670_COM3, 0x00},   {OV7670_COM14, 0x00}, {0x72, 0x11}, /* downsample by 4 */
@@ -428,8 +449,8 @@ static const struct video_reg8 ov7675_regs_vga[] = {
 static const struct video_reg8 ov7675_regs_qvga[] = {
 	{OV7670_COM3, OV7675_COM3_DCW_EN},
 	{OV7670_COM14, 0x11}, /* Divide by 2 */
-	{0x72, 0x22},         /* This has no effect on OV7675 */
-	{0x73, 0xf2},         /* This has no effect on OV7675 */
+	{0x72, 0x22},
+	{0x73, 0xf2},
 	{OV7670_HSTART, 0x15},
 	{OV7670_HSTOP, 0x03},
 	{OV7670_HREF, 0xC0},
@@ -441,15 +462,16 @@ static const struct video_reg8 ov7675_regs_qvga[] = {
 static const struct video_reg8 ov7675_regs_qqvga[] = {
 	{OV7670_COM3, OV7675_COM3_DCW_EN},
 	{OV7670_COM14, 0x11}, /* Divide by 2 */
-	{0x72, 0x22},         /* This has no effect on OV7675*/
-	{0x73, 0xf2},         /* This has no effect on OV7675*/
+	{0x72, 0x22},
+	{0x73, 0xf2},
 	{OV7670_HSTART, 0x16},
 	{OV7670_HSTOP, 0x04},
 	{OV7670_HREF, 0xa4},
 	{OV7670_VSTRT, 0x22},
 	{OV7670_VSTOP, 0x7a},
 	{OV7670_VREF, 0xfa},
 };
+#endif
 
 static int ov767x_get_caps(const struct device *dev, struct video_caps *caps)
 {
@@ -466,9 +488,26 @@ static int ov767x_set_fmt(const struct device *dev, struct video_format *fmt)
 	int ret = -ENOTSUP;
 	uint8_t i = 0U;
 
-	if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565 && fmt->pixelformat != VIDEO_PIX_FMT_YUYV) {
-		LOG_ERR("Only RGB565 and YUYV supported!");
-		return -ENOTSUP;
+	if (!memcmp(&data->fmt, fmt, sizeof(data->fmt))) {
+		/* nothing to do */
+		return 0;
+	}
+
+	/* Set RGB Format */
+	if (fmt->pixelformat == VIDEO_PIX_FMT_RGB565) {
+		ret = video_write_cci_multiregs8(&config->bus, ov7670_rgb565_regs,
+						 ARRAY_SIZE(ov7670_rgb565_regs));
+	} else if (fmt->pixelformat == VIDEO_PIX_FMT_YUYV) {
+		ret = video_write_cci_multiregs8(&config->bus, ov767x_yuv422_regs,
+						 ARRAY_SIZE(ov767x_yuv422_regs));
+	} else {
+		LOG_ERR("Image format not supported");
+		ret = -ENOTSUP;
+	}
+
+	if (ret < 0) {
+		LOG_ERR("Format not set!");
+		return ret;
 	}
 
 	if (!memcmp(&data->fmt, fmt, sizeof(data->fmt))) {
@@ -535,51 +574,107 @@ static int ov767x_set_fmt(const struct device *dev, struct video_format *fmt)
 			i++;
 		}
 	}
+	if (ret < 0) {
+		LOG_ERR("Resolution not supported!");
+		return ret;
+	}
 
-	if (config->camera_model == OV767X_MODEL_OV7675) {
-		while (config->fmts[i].pixelformat) {
-			if (config->fmts[i].width_min == fmt->width &&
-			    config->fmts[i].height_min == fmt->height &&
-			    config->fmts[i].pixelformat == fmt->pixelformat) {
-				/* Set output format */
-				switch (config->fmts[i].width_min) {
-				case 160: /* QQVGA */
-					ret = video_write_cci_multiregs8(
-						&config->bus, ov7675_regs_qqvga,
-						ARRAY_SIZE(ov7675_regs_qqvga));
-					break;
-				case 320: /* QVGA */
-					ret = video_write_cci_multiregs8(
-						&config->bus, ov7675_regs_qvga,
-						ARRAY_SIZE(ov7675_regs_qvga));
-					break;
-				case 640: /* VGA */
-					ret = video_write_cci_multiregs8(
-						&config->bus, ov7675_regs_vga,
-						ARRAY_SIZE(ov7675_regs_vga));
-					break;
-				default: /* QVGA */
-					ret = video_write_cci_multiregs8(
-						&config->bus, ov7675_regs_qvga,
-						ARRAY_SIZE(ov7675_regs_qvga));
-					break;
-				}
-				if (ret < 0) {
-					LOG_ERR("Resolution not set!");
-					return ret;
-				}
+	return 0;
+}
+#endif
+#if DT_HAS_COMPAT_STATUS_OKAY(ovti_ov7675)
+static int ov7675_set_fmt(const struct device *dev, struct video_format *fmt)
+{
+	const struct ov767x_config *config = dev->config;
+	struct ov767x_data *data = dev->data;
+	int ret = -ENOTSUP;
+	uint8_t i = 0U;
+
+	if (!memcmp(&data->fmt, fmt, sizeof(data->fmt))) {
+		/* nothing to do */
+		return 0;
+	}
+
+	/* Set RGB Format */
+	if (fmt->pixelformat == VIDEO_PIX_FMT_RGB565) {
+		ret = video_write_cci_multiregs8(&config->bus, ov7675_rgb565_regs,
+						 ARRAY_SIZE(ov7675_rgb565_regs));
+	} else if (fmt->pixelformat == VIDEO_PIX_FMT_YUYV) {
+		ret = video_write_cci_multiregs8(&config->bus, ov767x_yuv422_regs,
+						 ARRAY_SIZE(ov767x_yuv422_regs));
+	} else {
+		LOG_ERR("Image format not supported");
+		ret = -ENOTSUP;
+	}
+
+	if (ret < 0) {
+		LOG_ERR("Format not set!");
+		return ret;
+	}
+
+	while (config->fmts[i].pixelformat) {
+		if (config->fmts[i].width_min == fmt->width &&
+		    config->fmts[i].height_min == fmt->height &&
+		    config->fmts[i].pixelformat == fmt->pixelformat) {
+			/* Set output format */
+			switch (config->fmts[i].width_min) {
+			case 160: /* QQVGA */
+				ret = video_write_cci_multiregs8(&config->bus, ov7675_regs_qqvga,
+								 ARRAY_SIZE(ov7675_regs_qqvga));
+				break;
+			case 320: /* QVGA */
+				ret = video_write_cci_multiregs8(&config->bus, ov7675_regs_qvga,
+								 ARRAY_SIZE(ov7675_regs_qvga));
+				break;
+			case 640: /* VGA */
+				ret = video_write_cci_multiregs8(&config->bus, ov7675_regs_vga,
+								 ARRAY_SIZE(ov7675_regs_vga));
+				break;
+			default: /* QVGA */
+				ret = video_write_cci_multiregs8(&config->bus, ov7675_regs_qvga,
+								 ARRAY_SIZE(ov7675_regs_qvga));
+				break;
+			}
+			if (ret < 0) {
+				LOG_ERR("Resolution not set!");
+				return ret;
 			}
-			i++;
 		}
+		i++;
 	}
-
 	if (ret < 0) {
 		LOG_ERR("Resolution not supported!");
 		return ret;
 	}
 
 	return 0;
 }
+#endif
+
+static int ov767x_set_fmt(const struct device *dev, struct video_format *fmt)
+{
+	int ret;
+
+	if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565 && fmt->pixelformat != VIDEO_PIX_FMT_YUYV) {
+		LOG_ERR("Only RGB565 and YUYV supported!");
+		return -ENOTSUP;
+	}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(ovti_ov7670)
+	ret = ov7670_set_fmt(dev, fmt);
+	if (ret < 0) {
+		return ret;
+	}
+#endif
+#if DT_HAS_COMPAT_STATUS_OKAY(ovti_ov7675)
+	ret = ov7675_set_fmt(dev, fmt);
+	if (ret < 0) {
+		return ret;
+	}
+#endif
+
+	return 0;
+}
 
 static int ov767x_get_fmt(const struct device *dev, struct video_format *fmt)
 {
@@ -689,7 +784,9 @@ static int ov767x_init(const struct device *dev)
 	}
 	/* Delay after reset */
 	k_msleep(5);
+
 	ret = ov767x_set_fmt(dev, &fmt);
+
 	if (ret < 0) {
 		return ret;
 	}