drivers: dma_mcux_edma: Simplify cache attr macros

The dependency on the chosen node for dtcm can be expressed in Kconfig
language.

Cache we care about is CPU DCACHE, not the meaningless "MCUX Cache"

The macros can be reordered to be simpler by having only one level of
conditional (no nesting) instead of three levels.

Move this code closer in the file to where this cache attribute macro is
actually going to be used (the init macro) instead of randomly splitting
up the struct definitions at the top.

Signed-off-by: Declan Snyder <[email protected]>

Author: decsny

drivers/dma/Kconfig.mcux_edma

@@ -58,6 +58,7 @@ config DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS
 	bool "Use DTCM for DMA descriptors"
 	default y
 	depends on DT_HAS_NXP_IMX_DTCM_ENABLED
+	depends on $(dt_chosen_enabled,zephyr_dtcm)
 	help
 	  When this option is activated, the descriptors for DMA transfer are
 	  located in the DTCM (Data Tightly Coupled Memory).

drivers/dma/dma_mcux_edma.c

@@ -62,38 +62,6 @@ struct dma_mcux_edma_config {
 	edma_tcd_t (*tcdpool)[CONFIG_DMA_TCD_QUEUE_SIZE];
 };
 
-
-#if defined(CONFIG_HAS_MCUX_CACHE) || defined(CONFIG_HAS_MCUX_XCACHE)
-
-#ifdef CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS
-
-#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))
-#define EDMA_TCDPOOL_CACHE_ATTR __dtcm_noinit_section
-#else /* DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) */
-#error Selected DTCM for MCUX DMA descriptors but no DTCM section.
-#endif /* DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) */
-
-#elif defined(CONFIG_NOCACHE_MEMORY)
-#define EDMA_TCDPOOL_CACHE_ATTR __nocache
-#else
-/*
- * Note: the TCD pool *must* be in non cacheable memory. All of the NXP SOCs
- * that support caching memory have their default SRAM regions defined as a
- * non cached memory region, but if the default SRAM region is changed EDMA
- * TCD pools would be moved to cacheable memory, resulting in DMA cache
- * coherency issues.
- */
-
-#define EDMA_TCDPOOL_CACHE_ATTR
-
-#endif /* CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS */
-
-#else /* CONFIG_HAS_MCUX_CACHE */
-
-#define EDMA_TCDPOOL_CACHE_ATTR
-
-#endif /* CONFIG_HAS_MCUX_CACHE */
-
 struct dma_mcux_channel_transfer_edma_settings {
 	uint32_t source_data_size;
 	uint32_t dest_data_size;
@@ -1021,6 +989,24 @@ static int dma_mcux_edma_init(const struct device *dev)
 #define DMA_TCD_ALIGN_SIZE	32
 #endif
 
+/*
+ * Note: the TCD pool *must* be in non cacheable memory. All of the NXP SOCs
+ * that support caching memory have their default SRAM regions defined as a
+ * non cached memory region, but if the default SRAM region is changed EDMA
+ * TCD pools would be moved to cacheable memory, resulting in DMA cache
+ * coherency issues.
+ */
+#if !defined(CONFIG_CPU_HAS_DCACHE)
+/* no cache means no worries */
+#define EDMA_TCDPOOL_CACHE_ATTR
+#elif defined(CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS)
+#define EDMA_TCDPOOL_CACHE_ATTR __dtcm_noinit_section
+#elif defined(CONFIG_NOCACHE_MEMORY)
+#define EDMA_TCDPOOL_CACHE_ATTR __nocache
+#else
+#error Unexpected or disallowed cache situation for dma descriptors
+#endif
+
 /*
  * define the dma
  */