drivers: eth_stm32_hal: adjust ptp clock rate based on nominal frequency

Adjusted ptp clock rate based on nominal frequency.

Signed-off-by: Yangbo Lu <[email protected]>

Author: yangbolu1991

drivers/ethernet/eth_stm32_hal.c

@@ -1503,25 +1503,15 @@ static int ptp_clock_stm32_rate_adjust(const struct device *dev, double ratio)
 	int key, ret;
 	uint32_t addend_val;
 
-	/* No change needed */
-	if (ratio == 1.0L) {
-		return 0;
-	}
-
 	key = irq_lock();
 
-	ratio *= (double)eth_dev_data->clk_ratio_adj;
-
 	/* Limit possible ratio */
 	if (ratio * 100 < CONFIG_ETH_STM32_HAL_PTP_CLOCK_ADJ_MIN_PCT ||
 			ratio * 100 > CONFIG_ETH_STM32_HAL_PTP_CLOCK_ADJ_MAX_PCT) {
 		ret = -EINVAL;
 		goto error;
 	}
 
-	/* Save new ratio */
-	eth_dev_data->clk_ratio_adj = ratio;
-
 	/* Update addend register */
 	addend_val = UINT32_MAX * (double)eth_dev_data->clk_ratio * ratio;
 
@@ -1619,12 +1609,10 @@ static int ptp_stm32_init(const struct device *port)
 	 * clk_ratio is a ratio between desired PTP clock frequency and HCLK rate.
 	 * Because HCLK is defined by a physical oscillator, it might drift due
 	 * to manufacturing tolerances and environmental effects (e.g. temperature).
-	 * clk_ratio_adj compensates for such inaccuracies. It starts off as 1.0
-	 * and gets adjusted by calling ptp_clock_stm32_rate_adjust().
+	 * It gets adjusted by calling ptp_clock_stm32_rate_adjust().
 	 */
-	eth_dev_data->clk_ratio_adj = 1.0f;
 	addend_val =
-		UINT32_MAX * eth_dev_data->clk_ratio * eth_dev_data->clk_ratio_adj;
+		UINT32_MAX * eth_dev_data->clk_ratio;
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
 	heth->Instance->MACTSAR = addend_val;
 	heth->Instance->MACTSCR |= ETH_MACTSCR_TSADDREG;

drivers/ethernet/eth_stm32_hal_priv.h

@@ -60,7 +60,6 @@ struct eth_stm32_hal_dev_data {
 #if defined(CONFIG_PTP_CLOCK_STM32_HAL)
 	const struct device *ptp_clock;
 	float clk_ratio;
-	float clk_ratio_adj;
 #endif /* CONFIG_PTP_CLOCK_STM32_HAL */
 #if defined(CONFIG_NET_STATISTICS_ETHERNET)
 	struct net_stats_eth stats;