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boards: WeAct: Add STM32F405 Core board
The WeAct STM32F405 Core Board is an extremely low cost and bare-bones development board featuring the STM32F405RG, 64-pin variant of the STM32F405x series. Signed-off-by: Pavlo Yadvychuk <[email protected]>
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‎boards/weact/stm32f405_core/Kconfig.weact_stm32f405_core‎

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# Copyright (c) 2024 Pavlo Yadvychuk
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_WEACT_STM32F405_CORE
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select SOC_STM32F405XX

‎boards/weact/stm32f405_core/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
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board_runner_args(jlink "--device=STM32F405RG" "--speed=4000")
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include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/weact/stm32f405_core/board.yml‎

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board:
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name: weact_stm32f405_core
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vendor: weact
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socs:
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- name: stm32f405xx

‎boards/weact/stm32f405_core/doc/img/stm32f405_core.jpg‎

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‎boards/weact/stm32f405_core/doc/index.rst‎

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.. _weact_stm32f405_core:
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WeAct Studio STM32F405 Core Board V1.0
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######################################
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Overview
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********
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The WeAct STM32F405 Core Board is an extremely low cost and bare-bones
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development board featuring the STM32F405RG, see `STM32F405RG website`_.
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This is the 64-pin variant of the STM32F405x series,
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see `STM32F405x reference manual`_. More info about the board available
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on `WeAct Github`_.
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.. image:: img/stm32f405_core.jpg
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:align: center
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:alt: STM32F405 Core Board v1.0
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Hardware
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********
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The STM32F405RG based Core V1.0 Board provides the following
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hardware components:
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- STM32F405RG in QFPN64 package
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- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time
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accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory
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- 168 MHz max CPU frequency
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- VDD from 1.7 V to 3.6 V
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- 1 MB Flash
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- 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory)
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- GPIO with external interrupt capability
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- 3x12-bit, 2.4 MSPS ADC up to 24 channels and 7.2 MSPS in triple interleaved mode
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- 2x12-bit D/A converters
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- 16-stream DMA controller
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- Up to 17 Timers (twelve 16-bit, two 32-bit, two watchdog timers and a SysTick timer)
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- USART/UART (4)
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- I2C (3)
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- SPI/I2S (3)
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- CAN (2)
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- SDIO
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- USB 2.0 full-speed device/host/OTG controller with on-chip PHY
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- USB 2.0 high-speed/full-speed device/host/OTG controller with on-chip full-speed PHY and ULPI
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- 10/100 Ethernet MAC
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- CRC calculation unit
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- 96-bit unique ID
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- RTC with hardware calendar
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- 8- to 14-bit parallel camera interface
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- LCD parallel interface, 8080/6800 modes
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Supported Features
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==================
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The Zephyr weact_stm32f405_core board configuration supports the following
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hardware features:
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+------------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+============+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+------------+------------+-------------------------------------+
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| SYSTICK | on-chip | system clock |
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+------------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+------------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+------------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+------------+------------+-------------------------------------+
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| FLASH | on-chip | flash |
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+------------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+------------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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+------------+------------+-------------------------------------+
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| ADC | on-chip | ADC Controller |
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+------------+------------+-------------------------------------+
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| USB OTG FS | on-chip | USB device |
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+------------+------------+-------------------------------------+
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The default configuration can be found in
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:zephyr_file:`boards/weact/stm32f405_core/weact_stm32f405_core_defconfig`
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Pin Mapping
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===========
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- UART_1 TX/RX : PA9/PA10
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- UART_2 TX/RX : PA2/PA3
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- I2C1 SCL/SDA : PB6/PB7
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- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7
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- CAN1 TX/RX : Pb9/PB8
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- SDMMC1 D0..D4/CLK/CMD : PC8/PC9/PC10/PC11/PC12/PD2
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- USER_PB : PC13
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- USER_LED : PB2
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Clock Sources
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-------------
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The board has two external oscillators. The frequency of the slow clock (LSE) is
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32.768 kHz. The frequency of the main clock (HSE) is 8 MHz.
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The default configuration sources the system clock from the PLL, which is
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derived from HSE, and is set at 168MHz, which is the maximum possible frequency
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to achieve a stable USB clock (48MHz).
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Programming and Debugging
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*************************
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There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
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bootloader, and another by using the SWD debug port (which requires additional
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hardware). Flashing using the ROM bootloader requires a special activation
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pattern, which can be triggered by using the BOOT0 pin.
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Flashing
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========
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Installing dfu-util
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-------------------
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It is recommended to use at least v0.8 of `dfu-util`_. The package available in
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debian/ubuntu can be quite old, so you might have to build dfu-util from source.
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There is also a Windows version which works, but you may have to install the
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right USB drivers with a tool like `Zadig`_.
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Flashing an Application
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-----------------------
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Connect a USB-C cable and the board should power ON. Force the board into DFU mode
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by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch.
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The dfu-util runner is supported on this board and so a sample can be built and
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tested easily.
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.. zephyr-app-commands::
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:zephyr-app: samples/basic/blinky
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:board: weact_stm32f405_core
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:goals: build flash
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.. zephyr-app-commands::
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:zephyr-app: samples/basic/button
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:board: weact_stm32f405_core
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:goals: build flash
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.. zephyr-app-commands::
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:zephyr-app: samples/subsys/fs/fs_sample
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:board: weact_stm32f405_core
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:goals: build flash
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Debugging
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=========
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The board can be debugged by installing the included 100 mil (0.1 inch) header,
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and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO
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pins on that header.
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References
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**********
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.. target-notes::
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.. _board release notes:
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https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard/blob/master/README.md
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.. _Zadig:
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https://zadig.akeo.ie/
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.. _WeAct Github:
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https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard
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.. _dfu-util:
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http://dfu-util.sourceforge.net/build.html
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.. _STM32F405RG website:
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https://www.st.com/en/microcontrollers-microprocessors/stm32f405rg.html
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.. _STM32F405x reference manual:
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https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

‎boards/weact/stm32f405_core/support/openocd.cfg‎

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source [find interface/stlink.cfg]
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transport select hla_swd
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source [find target/stm32f4x.cfg]
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reset_config srst_only
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$_TARGETNAME configure -event gdb-attach {
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echo "Debugger attaching: halting execution"
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reset halt
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gdb_breakpoint_override hard
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}
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$_TARGETNAME configure -event gdb-detach {
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echo "Debugger detaching: resuming execution"
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resume
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}

‎boards/weact/stm32f405_core/weact_stm32f405_core.dts‎

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/*
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* Copyright (c) 2024 Pavlo Yadvychuk
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/f4/stm32f405Xg.dtsi>
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#include <st/f4/stm32f405rgtx-pinctrl.dtsi>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "WeAct Studio STM32F405 Core Board";
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compatible = "weact,stm32f405-core", "st,stm32f405";
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chosen {
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zephyr,console = &usart1;
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zephyr,shell-uart = &usart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,ccm = &ccm0;
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};
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leds {
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compatible = "gpio-leds";
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led: led {
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gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
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label = "User LED";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button: button {
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label = "User";
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gpios = <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
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zephyr,code = <INPUT_KEY_0>;
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};
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};
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aliases {
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led0 = &led;
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sw0 = &user_button;
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watchdog0 = &iwdg;
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sdhc0 = &sdmmc1;
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};
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};
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&clk_lsi {
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status = "okay";
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};
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&clk_hse {
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clock-frequency = <DT_FREQ_M(8)>;
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status = "okay";
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};
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&pll {
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div-m = <8>;
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mul-n = <336>;
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div-p = <2>;
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div-q = <7>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(168)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <4>;
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apb2-prescaler = <2>;
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};
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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&usart2 {
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pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <I2C_BITRATE_FAST>;
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};
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&spi1 {
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pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
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pinctrl-names = "default";
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status = "okay";
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};
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&can1 {
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pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdmmc1 {
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status = "okay";
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pinctrl-0 = <&sdio_d0_pc8 &sdio_d1_pc9
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&sdio_d2_pc10 &sdio_d3_pc11
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&sdio_ck_pc12 &sdio_cmd_pd2>;
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pinctrl-names = "default";
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cd-gpios = <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
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};
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&rtc {
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
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<&rcc STM32_SRC_LSI RTC_SEL(2)>;
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status = "okay";
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};
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zephyr_udc0: &usbotg_fs {
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pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
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pinctrl-names = "default";
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status = "okay";
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};
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&iwdg {
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status = "okay";
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};
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&backup_sram {
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status = "okay";
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};

‎boards/weact/stm32f405_core/weact_stm32f405_core.yaml‎

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identifier: weact_stm32f405_core
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name: WeAct Studio STM32F405 Core Board
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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ram: 128
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flash: 1024
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supported:
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- counter
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- spi
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- i2c
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- uart
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- usb
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- can
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- gpio
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- watchdog
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- backup_sram
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vendor: weact

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