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Shreehari-AlifSemicfriedt
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include: zephyr: drivers: i3c: add open-drain timing configuration
This commit adds the I3C handling of open-drain timing configurations with the following changes: - Add scl_od_min structure to i3c_config_controller for high/low period settings - Define Open-drain mixed bus SCL timing constants Requirement (MIPI Specification for I3C Basic v1.2 (16-Dec-2024), Section 4.3.11.2 & Table 49): - The MIPI I3C specification mandates different open-drain speeds during bus initialization as defined in "I3C Basic Open Drain Timing Parameters". - The first broadcast address (7'h7E+W) must be transmitted at a slower open-drain speed to ensure visibility to all devices on the I3C bus, including legacy I2C devices. This slow speed (minimum 200ns Thigh) allows I2C devices to properly detect the I3C mode transition and disable their spike filters before switching to I3C mode. After the initial broadcast, normal I3C open-drain speeds can be used for regular operation. Signed-off-by: Shreehari HK <[email protected]>
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include/zephyr/drivers/i3c.h

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@@ -42,6 +42,14 @@
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extern "C" {
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#endif
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/**
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* @brief Max and min Open Drain timings.
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* Standard I3C SDR and I2C FM speed
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*/
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#define I3C_OD_TLOW_MIN_NS 200
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#define I3C_OD_MIXED_BUS_THIGH_MAX_NS 41
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#define I3C_OD_FIRST_BC_THIGH_MIN_NS 200
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/**
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* @name Bus Characteristic Register (BCR)
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* @anchor I3C_BCR
@@ -464,6 +472,22 @@ struct i3c_config_controller {
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uint32_t i2c;
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} scl;
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struct {
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/**
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* Requested minimum SCL Open Drain High period in Nanoseconds
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*
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* Note:
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* - For the first broadcast message, spec requires tHIGH_OD >= 200 ns.
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* - For normal messages, tHIGH_OD must not exceed 41 ns (spec max).
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*/
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uint32_t high_ns;
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/**
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* Requested minimum SCL Open-Drain LOW period in nanoseconds.
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*/
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uint32_t low_ns;
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} scl_od_min;
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/**
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* Bit mask of supported HDR modes (0 - 7).
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*

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