soc: esp32s3: AMP support

Updates and fixes to support APPCPU.
- fix ld scripts
- fix and update memory layout
- fix build issues
- fix sysbuild

Signed-off-by: Marek Matej <[email protected]>

Author: marekmatej

soc/espressif/common/loader.c

@@ -84,7 +84,6 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
 	unsigned int segments = 0;
 	unsigned int ram_segments = 0;
 
-	/* Using already fetched bootloader image header from bootloader_init */
 	offset += sizeof(esp_image_header_t);
 
 	while (segments++ < 16) {
@@ -223,7 +222,6 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
 			"IROM",
 			app_irom_start_aligned, app_irom_vaddr_aligned,
 			app_irom_size, app_irom_size);
-	ets_printf("\n\r");
 	esp_rom_uart_tx_wait_idle(0);
 }
 
@@ -248,7 +246,7 @@ void __start(void)
 	}
 #endif
 
-#ifndef CONFIG_MCUBOOT
+#if !defined(CONFIG_MCUBOOT) && !defined(CONFIG_SOC_ESP32S3_APPCPU)
 	map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size,
 			 _app_irom_start, _app_irom_vaddr, _app_irom_size);
 #endif

soc/espressif/esp32/Kconfig

@@ -32,8 +32,7 @@ config ESP32_APPCPU_DRAM
 config SOC_ENABLE_APPCPU
 	bool
 	default y
-	depends on IPM && SOC_ESP32_PROCPU
-	depends on MBOX && SOC_ESP32_PROCPU
+	depends on (IPM || MBOX) && SOC_ESP32_PROCPU
 	help
 	  This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
 

soc/espressif/esp32s3/CMakeLists.txt

@@ -1,14 +1,20 @@
 # SPDX-License-Identifier: Apache-2.0
 
 if (CONFIG_SOC_ESP32S3_APPCPU)
-  zephyr_sources(soc_appcpu.c)
+
+  zephyr_sources(
+    soc_appcpu.c
+    )
+
 else()
+
   zephyr_sources(
     soc.c
     soc_cache.c
     esp32s3-mp.c
     ../common/loader.c
     )
+
 endif()
 
 zephyr_include_directories(.)
@@ -22,13 +28,24 @@ zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
 # Get flash size to use in esptool as string
 math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
 
-# Make rom loader compatible binary file
-if(NOT CONFIG_BOOTLOADER_MCUBOOT)
+# Get UART baudrate from DT
+dt_chosen(dts_shell_uart PROPERTY "zephyr,shell-uart")
+if(${dts_shell_uart})
+  dt_prop(monitor_baud PATH ${dts_shell_uart} PROPERTY "current-speed")
+endif()
+
+board_runner_args(esp32 "--esp-monitor-baud=${monitor_baud}")
+
+message("-- Espressif HAL path: ${ESP_IDF_PATH}")
+
+# Select image processing
+
+if(CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT)
 
   if(CONFIG_BUILD_OUTPUT_BIN)
 
     set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("esptool path: ${ESPTOOL_PY}")
+    message("-- Use the esptool.py: ${ESPTOOL_PY}")
 
     set(ELF2IMAGE_ARG "")
     if(NOT CONFIG_MCUBOOT)
@@ -37,49 +54,35 @@ if(NOT CONFIG_BOOTLOADER_MCUBOOT)
 
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip esp32s3 elf2image ${ELF2IMAGE_ARG}
+      ARGS --chip ${CONFIG_SOC} elf2image ${ELF2IMAGE_ARG}
       --flash_mode dio --flash_freq 40m
       --flash_size ${esptoolpy_flashsize}MB
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
       ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-  endif()
-
-endif()
 
-## When building for APPCPU
-if (CONFIG_SOC_ESP32S3_APPCPU)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py
-      ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c
-      -a "esp32s3_appcpu_fw_array")
   endif()
 
-else()
-  ## Building for PROCPU
-
-  set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
+endif()
 
-  # Get code-partition boot address
+# Select the image origin depending on the boot configuration
+if(CONFIG_SOC_ESP32S3_APPCPU)
+  dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
+elseif(CONFIG_MCUBOOT)
   dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-  dt_reg_addr(boot_off PATH ${dts_partition_path})
-
-  # Get code-partition slot0 address
+elseif(CONFIG_ESP_SIMPLE_BOOT)
+  dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
+else()
   dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-  dt_reg_addr(img_0_off PATH ${dts_partition_path})
+endif()
 
-  if(CONFIG_BOOTLOADER_MCUBOOT)
-    board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
-  else()
-    board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
-  endif()
+dt_reg_addr(image_off PATH ${dts_partition_path})
+board_finalize_runner_args(esp32 "--esp-app-address=${image_off}")
 
-endif()
+message("-- Image partition ${dts_partition_path}")
 
+# Look for cross references between bootloader sections
 if(CONFIG_MCUBOOT)
-    # search from cross references between bootloader sections
+
     message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND

soc/espressif/esp32s3/Kconfig

@@ -14,28 +14,6 @@ config SOC_SERIES_ESP32S3
 
 if SOC_SERIES_ESP32S3
 
-config ESP32S3_APPCPU_IRAM
-	hex "ESP32S3 APPCPU IRAM size"
-	depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
-	default 0x20000
-	help
-	  Defines APPCPU IRAM area in bytes.
-
-config ESP32S3_APPCPU_DRAM
-	hex "ESP32S3 APPCPU DRAM size"
-	depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
-	default 0x10000
-	help
-	  Defines APPCPU DRAM area in bytes.
-
-config SOC_ENABLE_APPCPU
-	bool
-	default y
-	depends on IPM && SOC_ESP32S3_PROCPU
-	depends on MBOX && SOC_ESP32S3_PROCPU
-	help
-	  This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
-
 menu "Cache config"
 
 choice ESP32S3_INSTRUCTION_CACHE_SIZE
@@ -178,4 +156,6 @@ config MAC_BB_PD
 
 endmenu  # Cache config
 
+rsource "Kconfig.amp"
+
 endif # SOC_SERIES_ESP32S3

soc/espressif/esp32s3/Kconfig.amp

@@ -0,0 +1,31 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32S3
+
+menu "AMP config"
+
+config ESP32S3_APPCPU_IRAM_SIZE
+	hex "ESP32S3 APPCPU IRAM size"
+	depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
+	default 0x10000
+	help
+	  Defines APPCPU IRAM area size in bytes.
+
+config ESP32S3_APPCPU_DRAM_SIZE
+	hex "ESP32S3 APPCPU DRAM size"
+	depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
+	default 0x10000
+	help
+	  Defines APPCPU DRAM area size in bytes.
+
+config SOC_ENABLE_APPCPU
+	bool
+	default y
+	depends on (IPM || MBOX) && SOC_ESP32S3_PROCPU
+	help
+	  This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
+
+endmenu # AMP config
+
+endif # SOC_SERIES_ESP32S3

soc/espressif/esp32s3/Kconfig.defconfig

@@ -9,4 +9,7 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
 
+config BOOTLOADER_MCUBOOT
+	default y if SOC_ESP32S3_APPCPU
+
 endif # SOC_SERIES_ESP32S3

soc/espressif/esp32s3/default.ld

@@ -10,24 +10,16 @@
 
 #include "memory.h"
 
-/* The "user_iram_end" represents the 2nd stage bootloader
- * "iram_loader_seg" start address (that should not be overlapped).
- * If no bootloader is used, we can extend it to gain more user ram.
- */
-#ifdef CONFIG_ESP_SIMPLE_BOOT
-user_iram_end = (BOOTLOADER_USER_DRAM_END + IRAM_DRAM_OFFSET);
-#else
-user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
-#endif
-
 /* User available SRAM memory segments */
-user_dram_seg_org = SRAM1_DRAM_START;
-user_iram_seg_org = SRAM0_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE;
-user_dram_end = BOOTLOADER_IRAM_LOADER_SEG_START - IRAM_DRAM_OFFSET;
-user_idram_size = user_dram_end - SRAM1_DRAM_START;
-sram0_iram_size = SRAM0_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE;
-user_iram_seg_len = user_idram_size + sram0_iram_size;
-user_dram_seg_len = user_idram_size;
+amp_total_size = APPCPU_SRAM_TOTAL_SIZE;
+procpu_iram_end = USER_IRAM_END - APPCPU_SRAM_TOTAL_SIZE;
+procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_TOTAL_SIZE;
+
+procpu_iram_org = SRAM_USER_IRAM_START;
+procpu_iram_len = procpu_iram_end - procpu_iram_org;
+
+procpu_dram_org = SRAM1_DRAM_START;
+procpu_dram_len = procpu_dram_end - procpu_dram_org;
 
 /* Aliases */
 #define FLASH_CODE_REGION  irom0_0_seg
@@ -36,6 +28,7 @@ user_dram_seg_len = user_idram_size;
 #define RAMABLE_REGION     dram0_0_seg
 #define ROMABLE_REGION     FLASH
 
+/* Zephyr macro re-definitions */
 #undef GROUP_DATA_LINK_IN
 #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion
 
@@ -66,14 +59,13 @@ MEMORY
   FLASH (R):        org = 0x0, len = FLASH_SIZE - 0x100
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
-  iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len - APPCPU_IRAM_SIZE
-  dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len - APPCPU_DRAM_SIZE
+  iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len
+  dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len
 
   irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
   drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
 
-  /**
-   * `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
+  /* The `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
    * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
    */
 #if defined(CONFIG_ESP_SPIRAM)
@@ -101,11 +93,15 @@ MEMORY
 ENTRY(CONFIG_KERNEL_ENTRY)
 
 /* Used as a pointer to the heap end */
+#ifdef CONFIG_SOC_ENABLE_APPCPU
+_heap_sentry = procpu_dram_end;
+#else
 _heap_sentry = DRAM_RESERVED_START;
+#endif
 
 SECTIONS
 {
-  _iram_dram_offset =  IRAM_DRAM_OFFSET;
+  _iram_dram_offset = IRAM_DRAM_OFFSET;
 
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   /* Reserve space for MCUboot header in the binary */
@@ -116,6 +112,7 @@ SECTIONS
     QUAD(0x0)
     QUAD(0x0)
   } > mcuboot_hdr
+  /* Image load table */
   .metadata :
   {
     /* 0. Magic byte for load header */
@@ -144,7 +141,6 @@ SECTIONS
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
-
 /* Virtual non-loadable sections */
 #include <zephyr/linker/rel-sections.ld>
 
@@ -275,7 +271,9 @@ SECTIONS
     *(.entry.text)
     *(.init.literal)
     *(.init)
+
     _init_end = ABSOLUTE(.);
+
   } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
 
   .iram0.text : ALIGN(4)
@@ -310,6 +308,11 @@ SECTIONS
     *libphy.a:(.phyiram .phyiram.*)
     *libgcov.a:(.literal .text .literal.* .text.*)
 
+    /* APPCPU_ENABLED */
+    *libzephyr.a:esp32s3-mp.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:flash_mmap.*(.literal .text .literal.* .text.*)
+
     /* [mapping:esp_psram] */
     *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*)
     *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*)
@@ -550,6 +553,11 @@ SECTIONS
     *libzephyr.a:esp_mmu_map.*(.rodata .rodata.*)
     *libdrivers__interrupt_controller.a:(.rodata .rodata.*)
 
+    /* APPCPU_ENABLE */
+    *libzephyr.a:esp32s3-mp.*(.rodata .rodata.*)
+    *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
+    *libzephyr.a:flash_mmap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
+
     /* [mapping:esp_psram] */
     *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*)
     *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*)
@@ -798,6 +806,10 @@ SECTIONS
 
   } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
 
+  /* --- END OF IROM --- */
+
+  /* --- START OF DROM --- */
+
   /* This dummy section represents the .flash.text section but in default_rodata_seg.
    * Thus, it must have its alignment and (at least) its size.
    */
@@ -879,6 +891,10 @@ SECTIONS
     _image_rodata_end = ABSOLUTE(.);
   } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
 
+  /* --- END OF DROM --- */
+
+  /* --- START OF SPIRAM --- */
+
   /**
    * This section is required to skip flash rodata sections, because `ext_ram_seg`
    * and `drom0_0_seg` are on the same bus
@@ -907,8 +923,9 @@ SECTIONS
 
 #endif /* CONFIG_ESP_SPIRAM */
 
-  /* --- XTENSA GLUE AND DEBUG BEGIN --- */
+  /* --- END OF SPIRAM --- */
 
+  /* --- XTENSA GLUE AND DEBUG BEGIN --- */
 #ifdef CONFIG_GEN_ISR_TABLES
 #include <zephyr/linker/intlist.ld>
 #endif