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drivers: clock control: Add Clock Control support for RZ/N2L, T2M
Add Clock Control driver support for Renesas RZ/N2L, T2M Signed-off-by: Quang Le <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
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‎drivers/clock_control/CMakeLists.txt‎

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@@ -45,6 +45,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT clock_control_renesas_rx_root_cgc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PLL clock_control_renesas_rx_pll_cgc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PCLK clock_control_renesas_rx_pclk_cgc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CGC clock_control_renesas_rz_cgc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG clock_control_renesas_rz_cpg.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)

‎drivers/clock_control/Kconfig‎

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@@ -96,6 +96,8 @@ source "drivers/clock_control/Kconfig.renesas_rx_cgc"
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source "drivers/clock_control/Kconfig.renesas_rz_cpg"
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source "drivers/clock_control/Kconfig.renesas_rz_cgc"
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source "drivers/clock_control/Kconfig.max32"
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source "drivers/clock_control/Kconfig.ambiq"

‎drivers/clock_control/Kconfig.renesas_rz_cgc‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_RENESAS_RZ_CGC
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bool "Renesas RZ Clock Control Driver"
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default y
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depends on DT_HAS_RENESAS_RZ_CGC_ENABLED
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select USE_RZ_FSP_CGC
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help
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Enable support for Renesas RZ CGC Clock Generator Circuit (CGC) driver.
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The CGC driver supports only module's clocks.
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The PLLs and core clocks are not configured by the CGC driver.

‎drivers/clock_control/clock_control_renesas_rz_cgc.c‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/renesas_rztn_clock.h>
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#include <zephyr/kernel.h>
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#include "bsp_api.h"
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#define DT_DRV_COMPAT renesas_rz_cgc
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static int clock_control_renesas_rz_on(const struct device *dev, clock_control_subsys_t sys)
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{
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if (!dev || !sys) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
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uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
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switch (ip) {
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case RZ_IP_BSC:
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R_BSP_MODULE_START(FSP_IP_BSC, ch);
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break;
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case RZ_IP_XSPI:
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R_BSP_MODULE_START(FSP_IP_XSPI, ch);
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break;
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case RZ_IP_SCI:
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R_BSP_MODULE_START(FSP_IP_SCI, ch);
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break;
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case RZ_IP_IIC:
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R_BSP_MODULE_START(FSP_IP_IIC, ch);
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break;
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case RZ_IP_SPI:
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R_BSP_MODULE_START(FSP_IP_SPI, ch);
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break;
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case RZ_IP_GPT:
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R_BSP_MODULE_START(FSP_IP_GPT, ch);
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break;
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case RZ_IP_ADC12:
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R_BSP_MODULE_START(FSP_IP_ADC12, ch);
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break;
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case RZ_IP_CMT:
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R_BSP_MODULE_START(FSP_IP_CMT, ch);
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break;
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case RZ_IP_CMTW:
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R_BSP_MODULE_START(FSP_IP_CMTW, ch);
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break;
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case RZ_IP_CANFD:
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R_BSP_MODULE_START(FSP_IP_CANFD, ch);
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break;
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case RZ_IP_GMAC:
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R_BSP_MODULE_START(FSP_IP_GMAC, ch);
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break;
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case RZ_IP_ETHSW:
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R_BSP_MODULE_START(FSP_IP_ETHSW, ch);
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break;
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case RZ_IP_USBHS:
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R_BSP_MODULE_START(FSP_IP_USBHS, ch);
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break;
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case RZ_IP_RTC:
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R_BSP_MODULE_START(FSP_IP_RTC, ch);
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break;
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default:
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
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return -EINVAL; /* Invalid FSP IP Module */
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}
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
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return 0;
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}
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static int clock_control_renesas_rz_off(const struct device *dev, clock_control_subsys_t sys)
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{
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if (!dev || !sys) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
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uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
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switch (ip) {
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case RZ_IP_BSC:
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R_BSP_MODULE_STOP(FSP_IP_BSC, ch);
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break;
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case RZ_IP_XSPI:
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R_BSP_MODULE_STOP(FSP_IP_XSPI, ch);
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break;
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case RZ_IP_SCI:
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R_BSP_MODULE_STOP(FSP_IP_SCI, ch);
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break;
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case RZ_IP_IIC:
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R_BSP_MODULE_STOP(FSP_IP_IIC, ch);
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break;
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case RZ_IP_SPI:
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R_BSP_MODULE_STOP(FSP_IP_SPI, ch);
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break;
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case RZ_IP_GPT:
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R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
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break;
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case RZ_IP_ADC12:
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R_BSP_MODULE_STOP(FSP_IP_ADC12, ch);
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break;
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case RZ_IP_CMT:
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R_BSP_MODULE_STOP(FSP_IP_CMT, ch);
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break;
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case RZ_IP_CMTW:
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R_BSP_MODULE_STOP(FSP_IP_CMTW, ch);
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break;
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case RZ_IP_CANFD:
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R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
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break;
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case RZ_IP_GMAC:
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R_BSP_MODULE_STOP(FSP_IP_GMAC, ch);
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break;
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case RZ_IP_ETHSW:
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R_BSP_MODULE_STOP(FSP_IP_ETHSW, ch);
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break;
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case RZ_IP_USBHS:
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R_BSP_MODULE_STOP(FSP_IP_USBHS, ch);
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break;
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case RZ_IP_RTC:
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R_BSP_MODULE_STOP(FSP_IP_RTC, ch);
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break;
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default:
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
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return -EINVAL; /* Invalid FSP IP Module */
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}
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
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return 0;
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}
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static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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if (!dev || !sys || !rate) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
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uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
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*rate = clk_hz;
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return 0;
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}
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static DEVICE_API(clock_control, rz_clock_control_driver_api) = {
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.on = clock_control_renesas_rz_on,
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.off = clock_control_renesas_rz_off,
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.get_rate = clock_control_renesas_rz_get_rate,
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};
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static int clock_control_rz_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, clock_control_rz_init, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rz_clock_control_driver_api);

‎dts/bindings/clock/renesas,rz-cgc-pll.yaml‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RZ Clock Generator Circuit PLL Clock
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compatible: "renesas,rz-cgc-pll"
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include: [base.yaml]
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properties:
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state:
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type: string
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default: initial
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enum:
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- initial
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- standby
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- normal
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description: PLL1 state

‎dts/bindings/clock/renesas,rz-cgc-subclk.yaml‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RZ Clock Control Peripheral Sub-Clock
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compatible: "renesas,rz-cgc-subclk"
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include: [base.yaml]
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properties:
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clock-frequency:
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type: int
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default: 96000000
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enum:
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- 75000000
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- 96000000
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description: |
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Select clock frequency (Hz) when asynchronous serial clock is selected in SPI and SCI
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xspi-clk-frequency:
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type: int
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default: 12500000
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enum:
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- 133333333
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- 100000000
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- 50000000
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- 25000000
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- 12500000
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- 75000000
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- 37500000
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description: Select clock frequency (Hz) supplied to xSPI
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canfd-source:
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type: int
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default: 1
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enum:
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- 0
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- 1
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- 2
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description: |
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Select clock source supplied to CANFD
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- 0: PCLKCAN 80MHz
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- 1: PCLKCAN 40MHz
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- 2: PCLKM 100MHz
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eth-phy-source:
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type: string
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default: main
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enum:
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- "pll1"
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- "main"
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description: |
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25 MHz reference clock to the external Ethernet PHY.
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Clock source is selectable from main clock or frequency-dividing clock for PLL1.

‎dts/bindings/clock/renesas,rz-cgc-sys-clock.yaml‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RZ Clock Control System Clock
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compatible: "renesas,rz-cgc-sys-clock"
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include: [base.yaml]
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properties:
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clock-frequency:
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type: int
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default: 200000000
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enum:
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- 200000000
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- 150000000
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description: Select frequency of iclk.
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div:
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type: int
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default: 4
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enum:
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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description: |
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Prescale divider to calculate the subclock frequency from the
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system clock frequency.
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mul:
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type: int
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default: 1
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description: |
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Multiplier to calculate the subclock frequency from the
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system clock frequency.

‎dts/bindings/clock/renesas,rz-cgc.yml‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Renesas RZ Clock Generator Circuit
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Usage example:
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#include <zephyr/dt-bindings/clock/renesas_rztn_clock.h>
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sci0: sci@xxx {
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...
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channel = <0>;
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/* Cell encodes HWIP, channel, clock source */
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clocks = <&cgc RZ_CLOCK(RZ_IP_SCI, 0, RZ_CLOCK_PCLKSCI0)>;
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...
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}
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compatible: "renesas,rz-cgc"
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include: [base.yaml, clock-controller.yaml]
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properties:
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"#clock-cells":
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const: 1
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clock-cells:
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- clk-id

‎include/zephyr/drivers/clock_control/renesas_rz_cgc.h‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_
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#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_
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#include <zephyr/drivers/clock_control.h>
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#define RZ_CGC_SUBCLK_DIV(subclk) \
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UTIL_CAT(RZ_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(subclk)) \
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(DT_PROP(subclk, div))
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#define RZ_CGC_SUBCLK_MUL(subclk) \
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UTIL_CAT(RZ_CGC_MUL_, DT_NODE_FULL_NAME_UPPER_TOKEN(subclk)) \
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(DT_PROP(subclk, mul))
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#define RZ_CGC_DIV_CKIO(n) UTIL_CAT(BSP_CLOCKS_CKIO_ICLK_DIV, n)
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#define RZ_CGC_MUL_CPU0CLK(n) UTIL_CAT(BSP_CLOCKS_FSELCPU0_ICLK_MUL, n)
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#define RZ_CGC_MUL_CPU1CLK(n) UTIL_CAT(BSP_CLOCKS_FSELCPU1_ICLK_MUL, n)
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#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_ */

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