drivers: clock: stm32: add PLLSAI handling (common/F4/F7)

Add code handling the pllsai. It is similar to the pllsai1
pllsai2 which can be found on some other socs, except, depending
on the socs the fact that pllsai source can be or not common with
other plls and moreover it can also have additional DIV_DIVQ
and DIV_DIVR additional dividers.
Choice is made to add PLLSAI instead of add further support to
PLLSAI1, in order to stick to the proper naming of the PLLs.

Signed-off-by: Alain Volmat <[email protected]>

Author: Alain Volmat

drivers/clock_control/clock_stm32_ll_common.c

@@ -228,6 +228,41 @@ int enabled_clock(uint32_t src_clk)
 		}
 		break;
 #endif /* STM32_SRC_PLLI2S_R */
+#if defined(STM32_SRC_PLLSAI_P)
+	case STM32_SRC_PLLSAI_P:
+		if (!IS_ENABLED(STM32_PLLSAI_P_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_P */
+#if defined(STM32_SRC_PLLSAI_Q)
+	case STM32_SRC_PLLSAI_Q:
+		if (!IS_ENABLED(STM32_PLLSAI_Q_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_Q */
+#if defined(STM32_SRC_PLLSAI_DIVQ)
+	case STM32_SRC_PLLSAI_DIVQ:
+		if (!IS_ENABLED(STM32_PLLSAI_Q_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVQ */
+#if defined(STM32_SRC_PLLSAI_R)
+	case STM32_SRC_PLLSAI_R:
+		if (!IS_ENABLED(STM32_PLLSAI_R_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_R */
+#if defined(STM32_SRC_PLLSAI_DIVR)
+	case STM32_SRC_PLLSAI_DIVR:
+		if (!IS_ENABLED(STM32_PLLSAI_R_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVR */
 #if defined(STM32_SRC_PLLSAI1_P)
 	case STM32_SRC_PLLSAI1_P:
 		if (!IS_ENABLED(STM32_PLLSAI1_P_ENABLED)) {
@@ -497,6 +532,50 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 					      STM32_PLLI2S_R_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLI2S_R */
+#if defined(STM32_SRC_PLLSAI_P) && STM32_PLLSAI_P_ENABLED
+	case STM32_SRC_PLLSAI_P:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_P_DIVISOR);
+		break;
+#endif /* STM32_SRC_PLLSAI_P */
+#if defined(STM32_SRC_PLLSAI_Q) && STM32_PLLSAI_Q_ENABLED
+	case STM32_SRC_PLLSAI_Q:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_Q_DIVISOR);
+		break;
+#endif /* STM32_SRC_PLLSAI_Q */
+#if defined(STM32_SRC_PLLSAI_DIVQ) && STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED && \
+	defined(STM32_PLLSAI_DIVQ_DIVISOR)
+	case STM32_SRC_PLLSAI_DIVQ:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_Q_DIVISOR);
+		*rate /= STM32_PLLSAI_DIVQ_DIVISOR;
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVQ */
+#if defined(STM32_SRC_PLLSAI_R) && STM32_PLLSAI_R_ENABLED
+	case STM32_SRC_PLLSAI_R:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_R_DIVISOR);
+		break;
+#endif /* STM32_SRC_PLLSAI_R */
+#if defined(STM32_SRC_PLLSAI_DIVR) && STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED && \
+	defined(STM32_PLLSAI_DIVR_DIVISOR)
+	case STM32_SRC_PLLSAI_DIVR:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_R_DIVISOR);
+		*rate /= STM32_PLLSAI_DIVR_DIVISOR;
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVR */
 #if defined(STM32_SRC_PLLSAI1_P) & STM32_PLLSAI1_P_ENABLED
 	case STM32_SRC_PLLSAI1_P:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
@@ -762,6 +841,16 @@ static void set_up_plls(void)
 	}
 #endif /* STM32_PLLI2S_ENABLED */
 
+#if defined(STM32_PLLSAI_ENABLED)
+	config_pllsai();
+
+	/* Enable PLL */
+	LL_RCC_PLLSAI_Enable();
+	while (LL_RCC_PLLSAI_IsReady() != 1U) {
+		/* Wait for PLL ready */
+	}
+#endif /* STM32_PLLSAI_ENABLED */
+
 #if defined(STM32_PLLSAI1_ENABLED)
 	config_pllsai1();
 

drivers/clock_control/clock_stm32_ll_common.h

@@ -42,12 +42,23 @@
 #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v
 #define plli2sr(v) z_plli2s_r(v)
 
-#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
-#define z_pllsai1_m(v) LL_RCC_PLLSAI1M_DIV_ ## v
-#else
-#define z_pllsai1_m(v) LL_RCC_PLLM_DIV_ ## v
-#endif
-#define pllsai1m(v) z_pllsai1_m(v)
+#define z_pllsai_m(v) LL_RCC_PLLM_DIV_ ## v
+#define pllsaim(v) z_pllsai_m(v)
+
+#define z_pllsai_p(v) LL_RCC_PLLSAIP_DIV_ ## v
+#define pllsaip(v) z_pllsai_p(v)
+
+#define z_pllsai_q(v) LL_RCC_PLLSAIQ_DIV_ ## v
+#define pllsaiq(v) z_pllsai_q(v)
+
+#define z_pllsai_divq(v) LL_RCC_PLLSAIDIVQ_DIV_ ## v
+#define pllsaidivq(v) z_pllsai_divq(v)
+
+#define z_pllsai_r(v) LL_RCC_PLLSAIR_DIV_ ## v
+#define pllsair(v) z_pllsai_r(v)
+
+#define z_pllsai_divr(v) LL_RCC_PLLSAIDIVR_DIV_ ## v
+#define pllsaidivr(v) z_pllsai_divr(v)
 
 #define z_pllsai1_p(v) LL_RCC_PLLSAI1P_DIV_ ## v
 #define pllsai1p(v) z_pllsai1_p(v)
@@ -92,6 +103,10 @@ void config_pll2(void);
 #if defined(STM32_PLLI2S_ENABLED)
 void config_plli2s(void);
 #endif
+#if defined(STM32_PLLSAI_ENABLED)
+uint32_t get_pllsaisrc_frequency(void);
+void config_pllsai(void);
+#endif
 #if defined(STM32_PLLSAI1_ENABLED)
 uint32_t get_pllsai1src_frequency(void);
 void config_pllsai1(void);

drivers/clock_control/clock_stm32f2_f4_f7.c

@@ -169,6 +169,95 @@ void config_plli2s(void)
 
 #endif /* STM32_PLLI2S_ENABLED */
 
+#if defined(STM32_PLLSAI_ENABLED)
+
+/**
+ * @brief Return PLLSAI source
+ */
+__unused
+static uint32_t get_pllsai_source(void)
+{
+	/* Configure PLL source */
+	if (IS_ENABLED(STM32_PLLSAI_SRC_HSI)) {
+		return LL_RCC_PLLSOURCE_HSI;
+	} else if (IS_ENABLED(STM32_PLLSAI_SRC_HSE)) {
+		return LL_RCC_PLLSOURCE_HSE;
+	}
+
+	__ASSERT(0, "Invalid source");
+	return 0;
+}
+
+/**
+ * @brief Get the PLLSAI source frequency
+ */
+__unused
+uint32_t get_pllsaisrc_frequency(void)
+{
+	if (IS_ENABLED(STM32_PLLSAI_SRC_HSI)) {
+		return STM32_HSI_FREQ;
+	} else if (IS_ENABLED(STM32_PLLSAI_SRC_HSE)) {
+		return STM32_HSE_FREQ;
+	}
+
+	__ASSERT(0, "Invalid source");
+	return 0;
+}
+
+/**
+ * @brief Set up PLLSAI configuration
+ */
+__unused
+void config_pllsai(void)
+{
+	/*
+	 * In case there is no dedicated M_DIVISOR for PLLSAI, the input is shared
+	 * with PLL and PLLI2S. Ensure that if they exist, they have the same value
+	 */
+#if !defined(RCC_PLLSAICFGR_PLLSAIM)
+#if defined(STM32_PLL_M_DIVISOR) && (STM32_PLL_M_DIVISOR != STM32_PLLSAI_M_DIVISOR)
+#error "PLLSAI M divisor must have same value as PLL M divisor"
+#endif
+#endif
+
+#if STM32_PLLSAI_P_ENABLED
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+	LL_RCC_PLLSAI_ConfigDomain_48M(get_pllsai_source(),
+				       pllsaim(STM32_PLLSAI_M_DIVISOR),
+				       STM32_PLLSAI_N_MULTIPLIER,
+				       pllsaip(STM32_PLLSAI_P_DIVISOR));
+#else
+#error "PLLSAI do not have P output on this SOC"
+#endif
+#endif /* STM32_PLLSAI_P_ENABLED */
+
+#if STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED
+#if defined(RCC_PLLSAICFGR_PLLSAIQ)
+	LL_RCC_PLLSAI_ConfigDomain_SAI(get_pllsai_source(),
+				       pllsaim(STM32_PLLSAI_M_DIVISOR),
+				       STM32_PLLSAI_N_MULTIPLIER,
+				       pllsaiq(STM32_PLLSAI_Q_DIVISOR),
+				       pllsaidivq(STM32_PLLSAI_DIVQ_DIVISOR));
+#else
+#error "PLLSAI do not have Q output on this SOC"
+#endif
+#endif /* STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED */
+
+#if STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+	LL_RCC_PLLSAI_ConfigDomain_LTDC(get_pllsai_source(),
+					pllsaim(STM32_PLLSAI_M_DIVISOR),
+					STM32_PLLSAI_N_MULTIPLIER,
+					pllsair(STM32_PLLSAI_R_DIVISOR),
+					pllsaidivr(STM32_PLLSAI_DIVR_DIVISOR));
+#else
+#error "PLLSAI do not have R output on this SOC"
+#endif
+#endif /* STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED */
+}
+
+#endif /* STM32_PLLSAI_ENABLED */
+
 /**
  * @brief Activate default clocks
  */

include/zephyr/drivers/clock_control/stm32_clock_control.h

@@ -220,6 +220,30 @@
 #define STM32_PLLI2S_R_DIVISOR		DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay)
+#define STM32_PLLSAI_ENABLED	1
+#define STM32_PLLSAI_M_DIVISOR		DT_PROP(DT_NODELABEL(pllsai), div_m)
+#define STM32_PLLSAI_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pllsai), mul_n)
+#define STM32_PLLSAI_P_ENABLED		DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_p)
+#define STM32_PLLSAI_P_DIVISOR		DT_PROP_OR(DT_NODELABEL(pllsai), div_p, 1)
+#define STM32_PLLSAI_Q_ENABLED		DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_q)
+#define STM32_PLLSAI_DIVQ_ENABLED	DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divq)
+#if (STM32_PLLSAI_Q_ENABLED && !STM32_PLLSAI_DIVQ_ENABLED) || \
+	(!STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED)
+#error "On STM32F4/STM32F7, both div_q and div_divq must be present if one of them is present"
+#endif
+#define STM32_PLLSAI_Q_DIVISOR		DT_PROP_OR(DT_NODELABEL(pllsai), div_q, 1)
+#define STM32_PLLSAI_DIVQ_DIVISOR	DT_PROP_OR(DT_NODELABEL(pllsai), div_divq, 1)
+#define STM32_PLLSAI_R_ENABLED		DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_r)
+#define STM32_PLLSAI_DIVR_ENABLED	DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divr)
+#if (STM32_PLLSAI_R_ENABLED && !STM32_PLLSAI_DIVR_ENABLED) || \
+	(!STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED)
+#error "On STM32F4/STM32F7, both div_r and div_divr must be present if one of them is present"
+#endif
+#define STM32_PLLSAI_R_DIVISOR		DT_PROP_OR(DT_NODELABEL(pllsai), div_r, 1)
+#define STM32_PLLSAI_DIVR_DIVISOR	DT_PROP_OR(DT_NODELABEL(pllsai), div_divr, 1)
+#endif
+
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
 #define STM32_PLLSAI1_ENABLED	1
 #define STM32_PLLSAI1_M_DIVISOR		DT_PROP(DT_NODELABEL(pllsai1), div_m)
@@ -435,6 +459,19 @@
 
 #endif
 
+/** PLLSAI clock source */
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai), okay) && \
+	DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), clocks)
+#define DT_PLLSAI_CLOCKS_CTRL	DT_CLOCKS_CTLR(DT_NODELABEL(pllsai))
+#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
+#define STM32_PLLSAI_SRC_HSI	1
+#endif
+#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
+#define STM32_PLLSAI_SRC_HSE	1
+#endif
+
+#endif
+
 /** PLLSAI1 clock source */
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \
 	DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks)
@@ -467,6 +504,20 @@
 
 #endif
 
+/* On STM32F4 series - PLL and PLLSAI share the same source */
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) && \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
+	!DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
+#error "On STM32F4 series, PLL and PLLSAI must have the same source"
+#endif
+
+/* On STM32F7 series - PLL and PLLSAI share the same source */
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) && \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
+	!DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
+#error "On STM32F7 series, PLL and PLLSAI must have the same source"
+#endif
+
 /* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \

include/zephyr/dt-bindings/clock/stm32f4_clock.h

@@ -43,6 +43,13 @@
 #define STM32_SRC_TIMPCLK1	(STM32_SRC_CK48 + 1)
 #define STM32_SRC_TIMPCLK2	(STM32_SRC_TIMPCLK1 + 1)
 
+/* PLLSAI clocks */
+#define STM32_SRC_PLLSAI_P	(STM32_SRC_TIMPCLK2 + 1)
+#define STM32_SRC_PLLSAI_Q	(STM32_SRC_PLLSAI_P + 1)
+#define STM32_SRC_PLLSAI_DIVQ	(STM32_SRC_PLLSAI_Q + 1)
+#define STM32_SRC_PLLSAI_R	(STM32_SRC_PLLSAI_DIVQ + 1)
+#define STM32_SRC_PLLSAI_DIVR	(STM32_SRC_PLLSAI_R + 1)
+
 /* I2S_CKIN not supported yet */
 /* #define STM32_SRC_I2S_CKIN	TBD */
 

include/zephyr/dt-bindings/clock/stm32f7_clock.h

@@ -42,6 +42,13 @@
 
 #define STM32_SRC_PLLI2S_R      (STM32_SRC_TIMPCLK2 + 1)
 
+/* PLLSAI clocks */
+#define STM32_SRC_PLLSAI_P	(STM32_SRC_PLLI2S_R + 1)
+#define STM32_SRC_PLLSAI_Q	(STM32_SRC_PLLSAI_P + 1)
+#define STM32_SRC_PLLSAI_DIVQ	(STM32_SRC_PLLSAI_Q + 1)
+#define STM32_SRC_PLLSAI_R	(STM32_SRC_PLLSAI_DIVQ + 1)
+#define STM32_SRC_PLLSAI_DIVR	(STM32_SRC_PLLSAI_R + 1)
+
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG		0x08