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Raffael Rostagnonashif
Raffael Rostagno
authored and
nashif
committed
drivers: intc: esp32c2: Added support
Added support for ESP32C2 and ESP8684 Signed-off-by: Raffael Rostagno <[email protected]>
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-3
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+213
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lines changed

‎drivers/interrupt_controller/Kconfig.esp32

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ config INTC_ESP32
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bool "Interrupt allocator for Xtensa-based Espressif SoCs"
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default y
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depends on SOC_FAMILY_ESPRESSIF_ESP32
10-
depends on !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
10+
depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
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help
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Enable custom interrupt allocator for Espressif SoCs based on Xtensa
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architecture.

‎drivers/interrupt_controller/Kconfig.esp32c3

Lines changed: 1 addition & 1 deletion
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@@ -4,7 +4,7 @@
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config INTC_ESP32C3
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bool "ESP32C3 interrupt controller driver"
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depends on SOC_FAMILY_ESPRESSIF_ESP32
7-
depends on SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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default y
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help
1010
Enables the esp32c3 interrupt controller driver to handle ISR

‎drivers/interrupt_controller/intc_esp32c3.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ static uint8_t esp_intr_irq_alloc[ESP32C6_INTC_AVAILABLE_IRQS][ESP32C6_INTC_SRCS
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static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0};
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71-
#if defined(CONFIG_SOC_SERIES_ESP32C3)
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#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
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static uint32_t esp_intr_find_irq_for_source(uint32_t source)
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{

‎include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h

Lines changed: 54 additions & 0 deletions
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@@ -0,0 +1,54 @@
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/*
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0
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#define WIFI_MAC_NMI_SOURCE 1
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#define WIFI_PWR_INTR_SOURCE 2
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#define WIFI_BB_INTR_SOURCE 3
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#define BT_MAC_INTR_SOURCE 4
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#define BT_BB_INTR_SOURCE 5
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#define BT_BB_NMI_SOURCE 6
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#define LP_TIMER_SOURCE 7
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#define COEX_SOURCE 8
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#define BLE_TIMER_SOURCE 9
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#define BLE_SEC_SOURCE 10
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#define I2C_MASTER_SOURCE 11
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#define APB_CTRL_INTR_SOURCE 12
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#define GPIO_INTR_SOURCE 13
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#define GPIO_NMI_SOURCE 14
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#define SPI1_INTR_SOURCE 15
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#define SPI2_INTR_SOURCE 16
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#define UART0_INTR_SOURCE 17
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#define UART1_INTR_SOURCE 18
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#define LEDC_INTR_SOURCE 19
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#define EFUSE_INTR_SOURCE 20
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#define RTC_CORE_INTR_SOURCE 21
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#define I2C_EXT0_INTR_SOURCE 22
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#define TG0_T0_LEVEL_INTR_SOURCE 23
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#define TG0_WDT_LEVEL_INTR_SOURCE 24
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#define CACHE_IA_INTR_SOURCE 25
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28
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#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 29
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#define ICACHE_PRELOAD0_INTR_SOURCE 30
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#define ICACHE_SYNC0_INTR_SOURCE 31
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#define APB_ADC_INTR_SOURCE 32
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#define DMA_CH0_INTR_SOURCE 33
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#define SHA_INTR_SOURCE 34
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#define ECC_INTR_SOURCE 35
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#define FROM_CPU_INTR0_SOURCE 36
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#define FROM_CPU_INTR1_SOURCE 37
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#define FROM_CPU_INTR2_SOURCE 38
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#define FROM_CPU_INTR3_SOURCE 39
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#define ASSIST_DEBUG_INTR_SOURCE 40
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#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 41
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#define CACHE_CORE0_ACS_INTR_SOURCE 42
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#endif

‎include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
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/*
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
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10+
#define ESP_NOSIG ESP_SIG_INVAL
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#define ESP_SPICLK_OUT_MUX ESP_SPICLK_OUT
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#define ESP_SPIQ_IN 0
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#define ESP_SPIQ_OUT 0
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#define ESP_SPID_IN 1
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#define ESP_SPID_OUT 1
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#define ESP_SPIHD_IN 2
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#define ESP_SPIHD_OUT 2
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#define ESP_SPIWP_IN 3
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#define ESP_SPIWP_OUT 3
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#define ESP_SPICLK_OUT 4
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#define ESP_SPICS0_OUT 5
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#define ESP_U0RXD_IN 6
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#define ESP_U0TXD_OUT 6
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#define ESP_U0CTS_IN 7
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#define ESP_U0RTS_OUT 7
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#define ESP_U0DSR_IN 8
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#define ESP_U0DTR_OUT 8
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#define ESP_U1RXD_IN 9
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#define ESP_U1TXD_OUT 9
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#define ESP_U1CTS_IN 10
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#define ESP_U1RTS_OUT 10
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#define ESP_U1DSR_IN 11
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#define ESP_U1DTR_OUT 11
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#define ESP_SPIQ_MONITOR 15
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#define ESP_SPID_MONITOR 16
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#define ESP_SPIHD_MONITOR 17
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#define ESP_SPIWP_MONITOR 18
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#define ESP_SPICS1_OUT 19
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#define ESP_CPU_TESTBUS0 20
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#define ESP_CPU_TESTBUS1 21
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#define ESP_CPU_TESTBUS2 22
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#define ESP_CPU_TESTBUS3 23
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#define ESP_CPU_TESTBUS4 24
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#define ESP_CPU_TESTBUS5 25
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#define ESP_CPU_TESTBUS6 26
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#define ESP_CPU_TESTBUS7 27
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#define ESP_CPU_GPIO_IN0 28
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#define ESP_CPU_GPIO_OUT0 28
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#define ESP_CPU_GPIO_IN1 29
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#define ESP_CPU_GPIO_OUT1 29
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#define ESP_CPU_GPIO_IN2 30
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#define ESP_CPU_GPIO_OUT2 30
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#define ESP_CPU_GPIO_IN3 31
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#define ESP_CPU_GPIO_OUT3 31
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#define ESP_CPU_GPIO_IN4 32
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#define ESP_CPU_GPIO_OUT4 32
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#define ESP_CPU_GPIO_IN5 33
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#define ESP_CPU_GPIO_OUT5 33
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#define ESP_CPU_GPIO_IN6 34
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#define ESP_CPU_GPIO_OUT6 34
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#define ESP_CPU_GPIO_IN7 35
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#define ESP_CPU_GPIO_OUT7 35
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#define ESP_EXT_ADC_START 45
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#define ESP_LEDC_LS_SIG_OUT0 45
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#define ESP_LEDC_LS_SIG_OUT1 46
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#define ESP_LEDC_LS_SIG_OUT2 47
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#define ESP_LEDC_LS_SIG_OUT3 48
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#define ESP_LEDC_LS_SIG_OUT4 49
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#define ESP_LEDC_LS_SIG_OUT5 50
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#define ESP_RMT_SIG_IN0 51
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#define ESP_RMT_SIG_OUT0 51
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#define ESP_RMT_SIG_IN1 52
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#define ESP_RMT_SIG_OUT1 52
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#define ESP_I2CEXT0_SCL_IN 53
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#define ESP_I2CEXT0_SCL_OUT 53
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#define ESP_I2CEXT0_SDA_IN 54
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#define ESP_I2CEXT0_SDA_OUT 54
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#define ESP_FSPICLK_IN 63
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#define ESP_FSPICLK_OUT 63
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#define ESP_FSPIQ_IN 64
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#define ESP_FSPIQ_OUT 64
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#define ESP_FSPID_IN 65
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#define ESP_FSPID_OUT 65
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#define ESP_FSPIHD_IN 66
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#define ESP_FSPIHD_OUT 66
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#define ESP_FSPIWP_IN 67
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#define ESP_FSPIWP_OUT 67
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#define ESP_FSPICS0_IN 68
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#define ESP_FSPICS0_OUT 68
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#define ESP_FSPICS1_OUT 69
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#define ESP_FSPICS2_OUT 70
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#define ESP_FSPICS3_OUT 71
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#define ESP_FSPICS4_OUT 72
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#define ESP_FSPICS5_OUT 73
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#define ESP_EXTERN_PRIORITY_I 77
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#define ESP_EXTERN_PRIORITY_O 77
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#define ESP_EXTERN_ACTIVE_I 78
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#define ESP_EXTERN_ACTIVE_O 78
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#define ESP_GPIO_EVENT_MATRIX_IN0 79
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#define ESP_GPIO_TASK_MATRIX_OUT0 79
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#define ESP_GPIO_EVENT_MATRIX_IN1 80
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#define ESP_GPIO_TASK_MATRIX_OUT1 80
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#define ESP_GPIO_EVENT_MATRIX_IN2 81
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#define ESP_GPIO_TASK_MATRIX_OUT2 81
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#define ESP_GPIO_EVENT_MATRIX_IN3 82
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#define ESP_GPIO_TASK_MATRIX_OUT3 82
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#define ESP_BB_DIAG8_OUT 83
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#define ESP_BB_DIAG9_OUT 84
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#define ESP_BB_DIAG10_OUT 85
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#define ESP_BB_DIAG11_OUT 86
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#define ESP_BB_DIAG12_OUT 87
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#define ESP_BB_DIAG13_OUT 88
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#define ESP_ANT_SEL0 89
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#define ESP_ANT_SEL1 90
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#define ESP_ANT_SEL2 91
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#define ESP_ANT_SEL3 92
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#define ESP_ANT_SEL4 93
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#define ESP_ANT_SEL5 94
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#define ESP_ANT_SEL6 95
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#define ESP_ANT_SEL7 96
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#define ESP_SIG_IN_FUNC_97 97
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#define ESP_SIG_IN_FUNC97 97
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#define ESP_SIG_IN_FUNC_98 98
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#define ESP_SIG_IN_FUNC98 98
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#define ESP_SIG_IN_FUNC_99 99
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#define ESP_SIG_IN_FUNC99 99
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#define ESP_SIG_IN_FUNC_100 100
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#define ESP_SIG_IN_FUNC100 100
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#define ESP_BLE_DBG_SYNCERR 101
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#define ESP_BLE_DBG_SYNC_FOUND 102
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#define ESP_BLE_DBG_CH_IDX 103
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#define ESP_BLE_DBG_SYNC_WINDOW 104
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#define ESP_BLE_DBG_DATA_EN 105
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#define ESP_BLE_DBG_DATA 106
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#define ESP_BLE_DBG_PKT_TX_ON 107
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#define ESP_BLE_DBG_PKT_RX_ON 108
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#define ESP_BLE_DBG_TXRU_ON 109
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#define ESP_BLE_DBG_RXRU_ON 110
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#define ESP_BLE_DBG_LELC_ST0 111
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#define ESP_BLE_DBG_LELC_ST1 112
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#define ESP_BLE_DBG_LELC_ST2 113
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#define ESP_BLE_DBG_LELC_ST3 114
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#define ESP_BLE_DBG_CRCOK 115
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#define ESP_BLE_DBG_CLK_GPIO 116
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#define ESP_BLE_DBG_RADIO_START 117
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#define ESP_BLE_DBG_SEQUENCE_ON 118
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#define ESP_BLE_DBG_COEX_BT_ON 119
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#define ESP_BLE_DBG_COEX_WIFI_ON 120
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#define ESP_CLK_OUT_OUT1 123
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#define ESP_CLK_OUT_OUT2 124
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#define ESP_CLK_OUT_OUT3 125
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#define ESP_SIG_GPIO_OUT 128
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#define ESP_GPIO_MAP_DATE 0x2106190
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_ */

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