tests: drivers: build_all: Build Altera FPGA driver

Altera FPGA driver should be built on a regular basis to ensure
that there are no regressions

Signed-off-by: Hardeep Sharma <[email protected]>

Author: hardeepsharma95

tests/drivers/build_all/fpga/app.overlay

@@ -38,6 +38,18 @@
 			#include "spi.dtsi"
 		};
 	};
+
+	fpga0: bridges {
+		compatible = "altr,socfpga-agilex-bridge";
+		status = "okay";
+	};
+
+	sip_smc: smc {
+		compatible = "intel,socfpga-agilex-sip-smc";
+		method = "smc";
+		status = "okay";
+		zephyr,num-clients = <2>;
+	};
 };
 
 /* Put device specific modifications to properties or disabling of devices

tests/drivers/build_all/fpga/prj.conf

@@ -11,3 +11,8 @@ CONFIG_FPGA=y
 # iCE40 FPGAs on a single bus to 1.
 CONFIG_PINCTRL=n
 CONFIG_ICE40_FPGA=y
+CONFIG_ALTERA_AGILEX_BRIDGE_FPGA=y
+CONFIG_ARM_SIP_SVC_DRIVER=y
+CONFIG_ARM_SIP_SVC_SUBSYS=y
+CONFIG_ARM_SIP_SVC_SUBSYS_SINGLY_OPEN=y
+CONFIG_HEAP_MEM_POOL_SIZE=16384