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| 1 | +/* |
| 2 | + * Copyright (c) 2020 STMicroelectronics |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +/** |
| 8 | + * @file |
| 9 | + * @brief Exception/interrupt context helpers for Cortex-M CPUs |
| 10 | + * |
| 11 | + * Exception/interrupt context helpers. |
| 12 | + */ |
| 13 | + |
| 14 | +#ifndef ARM_CORTEX_M_SCB_H_ |
| 15 | +#define ARM_CORTEX_M_SCB_H_ |
| 16 | + |
| 17 | +#include <stdint.h> |
| 18 | +#include <cmsis_core.h> |
| 19 | + |
| 20 | +/* Define macro for SHCSR presence, as it's not directly a Kconfig option. |
| 21 | + * SHCSR is present in ARMv7-M (M3, M4, M7) and ARMv8-M (M23, M33) architectures. |
| 22 | + */ |
| 23 | +#if defined(CONFIG_CPU_CORTEX_M3) || \ |
| 24 | + defined(CONFIG_CPU_CORTEX_M4) || \ |
| 25 | + defined(CONFIG_CPU_CORTEX_M7) || \ |
| 26 | + defined(CONFIG_CPU_CORTEX_M23) || \ |
| 27 | + defined(CONFIG_CPU_CORTEX_M33) |
| 28 | +#define CPU_CORTEX_M_HAS_SHCSR 1 |
| 29 | +#endif |
| 30 | + |
| 31 | +/** |
| 32 | + * @brief Structure to store essential, mutable SCB register values for backup/restore. |
| 33 | + * |
| 34 | + * This structure explicitly lists the SCB registers that are safe and meaningful |
| 35 | + * to backup and restore for common system state management. It avoids volatile, |
| 36 | + * read-only, or write-only status bits that should not be directly restored. |
| 37 | + */ |
| 38 | +typedef struct { |
| 39 | +#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR) |
| 40 | + uint32_t vtor; /*/< Vector Table Offset Register */ |
| 41 | +#endif |
| 42 | + uint32_t aircr; /*/< Application Interrupt and Reset Control Register |
| 43 | + * (only modifiable bits) |
| 44 | + */ |
| 45 | + uint32_t scr; /*/< System Control Register */ |
| 46 | + uint32_t ccr; /*/< Configuration Control Register */ |
| 47 | + uint32_t shpr[4]; /*/< System Handler Priority Registers (SHPR1-SHPR4) */ |
| 48 | +#if defined(CPU_CORTEX_M_HAS_SHCSR) |
| 49 | + uint32_t shcsr; /*/< System Handler Control and State Register */ |
| 50 | +#endif |
| 51 | +} scb_context_t; |
| 52 | + |
| 53 | +/** |
| 54 | + * @name SCB Register Backup/Restore Functions |
| 55 | + * @brief Functions for saving and restoring mutable SCB register state. |
| 56 | + * @{ |
| 57 | + */ |
| 58 | + |
| 59 | +/** |
| 60 | + * @brief Backs up essential SCB registers into a provided context structure. |
| 61 | + * |
| 62 | + * This function reads the current values of critical System Control Block (SCB) |
| 63 | + * registers that are safe to backup and stores them into the `context` structure. |
| 64 | + * |
| 65 | + * @param context Pointer to an `scb_context_t` structure where the register |
| 66 | + * values will be stored. Must not be NULL. |
| 67 | + */ |
| 68 | +void scb_backup_registers(scb_context_t *context); |
| 69 | + |
| 70 | +/** |
| 71 | + * @brief Restores essential SCB registers from a provided context structure. |
| 72 | + * |
| 73 | + * This function writes the values from the `context` structure back to the |
| 74 | + * respective System Control Block (SCB) registers. |
| 75 | + * |
| 76 | + * @warning Extreme caution is advised when restoring SCB registers. Only |
| 77 | + * mutable registers are restored. Specifically, the ICSR register |
| 78 | + * is NOT restored directly due to its volatile nature and read-only/ |
| 79 | + * write-only bits. |
| 80 | + * |
| 81 | + * @param context Pointer to a `scb_context_t` structure containing the |
| 82 | + * register values to be restored. Must not be NULL. |
| 83 | + */ |
| 84 | +void scb_restore_registers(const scb_context_t *context); |
| 85 | + |
| 86 | +/** @} */ |
| 87 | + |
| 88 | +#endif /* ARM_CORTEX_M_SCB_H_ */ |
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