drivers: spi: dw: support enhanced SPI operation

Some Synopsys SPI controllers support the enhanced SPI operations and
the SPI transfers need to configure the transfer type, instruction
length and address length along with CTRLR0 FRF(frame format) update.

Signed-off-by: Younghyun Park <[email protected]>

Author: myguitar

drivers/spi/spi_dw.c

@@ -41,6 +41,8 @@ LOG_MODULE_REGISTER(spi_dw);
 #include <zephyr/drivers/pinctrl.h>
 #endif
 
+#define DW_HSSI_VER_102A		(0x3130322a)
+
 static inline bool spi_dw_is_slave(struct spi_dw_data *spi)
 {
 	return (IS_ENABLED(CONFIG_SPI_SLAVE) &&
@@ -213,6 +215,7 @@ static int spi_dw_configure(const struct device *dev,
 
 	if ((config->operation & SPI_TRANSFER_LSB) ||
 	    (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
+	     !IS_ENABLED(CONFIG_SPI_DW_HSSI) &&
 	     (config->operation & (SPI_LINES_DUAL |
 				   SPI_LINES_QUAD | SPI_LINES_OCTAL)))) {
 		LOG_ERR("Unsupported configuration");
@@ -248,6 +251,23 @@ static int spi_dw_configure(const struct device *dev,
 		ctrlr0 |= DW_SPI_CTRLR0_SRL;
 	}
 
+#if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
+	if (spi->version >= DW_HSSI_VER_102A) {
+		/* SPI frame format for Tx/Rx data */
+		switch (SPI_LINES_GET(config->operation)) {
+		case SPI_LINES_DUAL:
+			ctrlr0 |= DW_SPI_CTRLR0_SPI_DUAL;
+			break;
+		case SPI_LINES_QUAD:
+			ctrlr0 |= DW_SPI_CTRLR0_SPI_QUAD;
+			break;
+		case SPI_LINES_OCTAL:
+			ctrlr0 |= DW_SPI_CTRLR0_SPI_OCTAL;
+			break;
+		}
+	}
+#endif
+
 	/* Installing the configuration */
 	write_ctrlr0(dev, ctrlr0);
 
@@ -410,6 +430,23 @@ static int transceive(const struct device *dev,
 
 	write_ctrlr0(dev, reg_data);
 
+#if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
+	if (spi->version >= DW_HSSI_VER_102A) {
+		/* Enhanced SPI operation */
+		reg_data = read_spi_ctrlr0(dev);
+		reg_data &= ~DW_SPI_ESPI_CTRLR0_TRANS_TYPE_MASK;
+		reg_data |= FIELD_PREP(DW_SPI_ESPI_CTRLR0_TRANS_TYPE_MASK,
+				       SPI_TRANS_TYPE_FIELD_GET(config->operation));
+		reg_data &= ~DW_SPI_ESPI_CTRLR0_ADDR_L_MASK;
+		reg_data |= FIELD_PREP(DW_SPI_ESPI_CTRLR0_ADDR_L_MASK,
+				       SPI_ADDR_L_FIELD_GET(config->operation));
+		reg_data &= ~DW_SPI_ESPI_CTRLR0_INST_L_MASK;
+		reg_data |= FIELD_PREP(DW_SPI_ESPI_CTRLR0_INST_L_MASK,
+				       SPI_INST_L_FIELD_GET(config->operation));
+		write_spi_ctrlr0(dev, reg_data);
+	}
+#endif
+
 	/* Set buffers info */
 	spi_context_buffers_setup(&spi->ctx, tx_bufs, rx_bufs, spi->dfs);
 

drivers/spi/spi_dw.h

@@ -199,6 +199,18 @@ static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
 #if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
 /* TXFTLR setting. Only valid for Controller operation mode. */
 #define DW_SPI_TXFTLR_TXFTLR_SHIFT	(16)
+
+/* SPI Frame Format */
+#define DW_SPI_CTRLR0_SPI_FRF_SHIFT	(22)
+#define DW_SPI_CTRLR0_SPI_STANDARD	(0 << DW_SPI_CTRLR0_SPI_FRF_SHIFT)
+#define DW_SPI_CTRLR0_SPI_DUAL		(1 << DW_SPI_CTRLR0_SPI_FRF_SHIFT)
+#define DW_SPI_CTRLR0_SPI_QUAD		(2 << DW_SPI_CTRLR0_SPI_FRF_SHIFT)
+#define DW_SPI_CTRLR0_SPI_OCTAL		(3 << DW_SPI_CTRLR0_SPI_FRF_SHIFT)
+
+/* SPI_CTRLR0 settings */
+#define DW_SPI_ESPI_CTRLR0_INST_L_MASK		GENMASK(9, 8)
+#define DW_SPI_ESPI_CTRLR0_ADDR_L_MASK		GENMASK(5, 2)
+#define DW_SPI_ESPI_CTRLR0_TRANS_TYPE_MASK	GENMASK(1, 0)
 #endif
 
 #define DW_SPI_CTRLR0_SCPH		BIT(DW_SPI_CTRLR0_SCPH_BIT)

drivers/spi/spi_dw_regs.h

@@ -40,6 +40,7 @@ extern "C" {
 #define DW_SPI_REG_SSI_COMP_VERSION	(0x5c)
 #define DW_SPI_REG_DR			(0x60)
 #define DW_SPI_REG_RX_SAMPLE_DLY	(0xf0)
+#define DW_SPI_REG_SPI_CTRLR0		(0xf4)
 
 /* Register helpers */
 DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
@@ -53,6 +54,8 @@ DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
 DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
 DEFINE_MM_REG_WRITE(rx_sample_dly, DW_SPI_REG_RX_SAMPLE_DLY, 32)
 DEFINE_MM_REG_READ(rx_sample_dly, DW_SPI_REG_RX_SAMPLE_DLY, 32)
+DEFINE_MM_REG_WRITE(spi_ctrlr0, DW_SPI_REG_SPI_CTRLR0, 32)
+DEFINE_MM_REG_READ(spi_ctrlr0, DW_SPI_REG_SPI_CTRLR0, 32)
 
 #ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
 DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 32)