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drivers/clock_control: stm32: Add AHB3 bus support
AHB3 bus support is added for compatible series. Additionaly, fix condition for AHB2 support and fix formatting Signed-off-by: Erwan Gouriou <[email protected]> Signed-off-by: Piotr Mienkowski <[email protected]>
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‎drivers/clock_control/clock_stm32_ll_common.c‎

Lines changed: 50 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,11 @@ static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
7171
clk_init->APB1CLKDivider = apb1_prescaler(
7272
CONFIG_CLOCK_STM32_APB1_PRESCALER);
7373

74-
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
74+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
75+
!defined (CONFIG_SOC_SERIES_STM32G0X)
7576
clk_init->APB2CLKDivider = apb2_prescaler(
7677
CONFIG_CLOCK_STM32_APB2_PRESCALER);
77-
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
78+
#endif
7879
}
7980

8081
static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
@@ -95,14 +96,25 @@ static inline int stm32_clock_control_on(const struct device *dev,
9596
break;
9697
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
9798
defined(CONFIG_SOC_SERIES_STM32L5X) || \
98-
defined(CONFIG_SOC_SERIES_STM32F4X) && !defined(CONFIG_SOC_STM32F410RX) || \
99+
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \
99100
defined(CONFIG_SOC_SERIES_STM32F7X) || \
100101
defined(CONFIG_SOC_SERIES_STM32F2X) || \
101102
defined(CONFIG_SOC_SERIES_STM32WBX) || \
102103
defined(CONFIG_SOC_SERIES_STM32G4X)
103104
case STM32_CLOCK_BUS_AHB2:
104105
LL_AHB2_GRP1_EnableClock(pclken->enr);
105106
break;
107+
#endif /* CONFIG_SOC_SERIES_STM32_* */
108+
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
109+
defined(CONFIG_SOC_SERIES_STM32L5X) || \
110+
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \
111+
defined(CONFIG_SOC_SERIES_STM32F7X) || \
112+
defined(CONFIG_SOC_SERIES_STM32F2X) || \
113+
defined(CONFIG_SOC_SERIES_STM32WBX) || \
114+
defined(CONFIG_SOC_SERIES_STM32G4X)
115+
case STM32_CLOCK_BUS_AHB3:
116+
LL_AHB3_GRP1_EnableClock(pclken->enr);
117+
break;
106118
#endif /* CONFIG_SOC_SERIES_STM32_* */
107119
case STM32_CLOCK_BUS_APB1:
108120
LL_APB1_GRP1_EnableClock(pclken->enr);
@@ -120,12 +132,13 @@ static inline int stm32_clock_control_on(const struct device *dev,
120132
case STM32_CLOCK_BUS_APB2:
121133
LL_APB2_GRP1_EnableClock(pclken->enr);
122134
break;
123-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
124-
#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
135+
#endif
136+
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \
137+
defined (CONFIG_SOC_SERIES_STM32G0X)
125138
case STM32_CLOCK_BUS_IOP:
126139
LL_IOP_GRP1_EnableClock(pclken->enr);
127140
break;
128-
#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */
141+
#endif
129142
default:
130143
return -ENOTSUP;
131144
}
@@ -147,14 +160,25 @@ static inline int stm32_clock_control_off(const struct device *dev,
147160
break;
148161
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
149162
defined(CONFIG_SOC_SERIES_STM32L5X) || \
150-
defined(CONFIG_SOC_SERIES_STM32F4X) && !defined(CONFIG_SOC_STM32F410RX) || \
163+
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \
151164
defined(CONFIG_SOC_SERIES_STM32F7X) || \
152165
defined(CONFIG_SOC_SERIES_STM32F2X) || \
153166
defined(CONFIG_SOC_SERIES_STM32WBX) || \
154167
defined(CONFIG_SOC_SERIES_STM32G4X)
155168
case STM32_CLOCK_BUS_AHB2:
156169
LL_AHB2_GRP1_DisableClock(pclken->enr);
157170
break;
171+
#endif /* CONFIG_SOC_SERIES_STM32_* */
172+
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
173+
defined(CONFIG_SOC_SERIES_STM32L5X) || \
174+
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \
175+
defined(CONFIG_SOC_SERIES_STM32F7X) || \
176+
defined(CONFIG_SOC_SERIES_STM32F2X) || \
177+
defined(CONFIG_SOC_SERIES_STM32WBX) || \
178+
defined(CONFIG_SOC_SERIES_STM32G4X)
179+
case STM32_CLOCK_BUS_AHB3:
180+
LL_AHB3_GRP1_EnableClock(pclken->enr);
181+
break;
158182
#endif /* CONFIG_SOC_SERIES_STM32_* */
159183
case STM32_CLOCK_BUS_APB1:
160184
LL_APB1_GRP1_DisableClock(pclken->enr);
@@ -172,12 +196,13 @@ static inline int stm32_clock_control_off(const struct device *dev,
172196
case STM32_CLOCK_BUS_APB2:
173197
LL_APB2_GRP1_DisableClock(pclken->enr);
174198
break;
175-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
176-
#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
199+
#endif
200+
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \
201+
defined (CONFIG_SOC_SERIES_STM32G0X)
177202
case STM32_CLOCK_BUS_IOP:
178203
LL_IOP_GRP1_DisableClock(pclken->enr);
179204
break;
180-
#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */
205+
#endif
181206
default:
182207
return -ENOTSUP;
183208
}
@@ -200,19 +225,22 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
200225
uint32_t ahb_clock = SystemCoreClock;
201226
uint32_t apb1_clock = get_bus_clock(ahb_clock,
202227
CONFIG_CLOCK_STM32_APB1_PRESCALER);
203-
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
228+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
229+
!defined (CONFIG_SOC_SERIES_STM32G0X)
204230
uint32_t apb2_clock = get_bus_clock(ahb_clock,
205231
CONFIG_CLOCK_STM32_APB2_PRESCALER);
206-
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
232+
#endif
207233

208234
ARG_UNUSED(clock);
209235

210236
switch (pclken->bus) {
211237
case STM32_CLOCK_BUS_AHB1:
212238
case STM32_CLOCK_BUS_AHB2:
213-
#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
239+
case STM32_CLOCK_BUS_AHB3:
240+
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \
241+
defined (CONFIG_SOC_SERIES_STM32G0X)
214242
case STM32_CLOCK_BUS_IOP:
215-
#endif /* (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) */
243+
#endif
216244
*rate = ahb_clock;
217245
break;
218246
case STM32_CLOCK_BUS_APB1:
@@ -232,11 +260,12 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
232260
#endif /* CONFIG_SOC_SERIES_STM32G0X */
233261
*rate = apb1_clock;
234262
break;
235-
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
263+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
264+
!defined (CONFIG_SOC_SERIES_STM32G0X)
236265
case STM32_CLOCK_BUS_APB2:
237266
*rate = apb2_clock;
238267
break;
239-
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
268+
#endif
240269
default:
241270
return -ENOTSUP;
242271
}
@@ -450,9 +479,10 @@ static int stm32_clock_control_init(const struct device *dev)
450479

451480
/* Set APB1 & APB2 prescaler*/
452481
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
453-
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
482+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
483+
!defined (CONFIG_SOC_SERIES_STM32G0X)
454484
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
455-
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
485+
#endif
456486

457487
/* If freq not increased, set flash latency after all clock setting */
458488
if (new_hclk_freq <= old_hclk_freq) {
@@ -543,7 +573,8 @@ static int stm32_clock_control_init(const struct device *dev)
543573

544574
/* Set APB1 & APB2 prescaler*/
545575
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
546-
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
576+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
577+
!defined (CONFIG_SOC_SERIES_STM32G0X)
547578
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
548579
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
549580

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