Skip to content

Commit 7c0f386

Browse files
Hieu Nguyentiennguyenzg
Hieu Nguyen
authored and
tiennguyenzg
committed
dts: renesas: Add DMA support for Renesas RZ/V2L, A3UL, T2M, N2L
Add DMA nodes to Renesas RZ/V2L, A3UL, T2M, N2L Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
1 parent d021ae7 commit 7c0f386

File tree

5 files changed

+190
-3
lines changed

5 files changed

+190
-3
lines changed

‎dts/arm/renesas/rz/rzg/r9a08g045.dtsi‎

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2024 EPAM Systems
3-
* Copyright (c) 2024 Renesas Electronics Corporation
3+
* Copyright (c) 2024-2025 Renesas Electronics Corporation
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

@@ -406,7 +406,7 @@
406406
};
407407

408408
dma0: dma@41800000 { /* Secure DMA */
409-
compatible = "renesas,rz-dma";
409+
compatible = "renesas,rz-dmac-b";
410410
reg = <0x41800000 0x800>, <0x41810000 0x20>;
411411
reg-names = "reg_main", "ext";
412412
interrupts = <95 1>, <96 1>, <97 1>, <98 1>,
@@ -419,9 +419,29 @@
419419
"ch8", "ch9", "ch10", "ch11",
420420
"ch12", "ch13", "ch14", "ch15",
421421
"err1";
422+
dma-unit = <0>;
423+
dma-channels = <16>;
424+
#dma-cells = <2>;
425+
status = "disabled";
426+
};
427+
428+
dma1: dma@41820000 { /* Secure DMA */
429+
compatible = "renesas,rz-dmac-b";
430+
reg = <0x41820000 0x800>, <0x41830000 0x20>;
431+
reg-names = "reg_main", "ext";
432+
interrupts = <112 1>, <113 1>, <114 1>, <115 1>,
433+
<116 1>, <117 1>, <118 1>, <119 1>,
434+
<120 1>, <121 1>, <122 1>, <123 1>,
435+
<124 1>, <125 1>, <126 1>, <127 1>,
436+
<111 1>; /* DMAERR1 */
437+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
438+
"ch4", "ch5", "ch6", "ch7",
439+
"ch8", "ch9", "ch10", "ch11",
440+
"ch12", "ch13", "ch14", "ch15",
441+
"err1";
442+
dma-unit = <1>;
422443
dma-channels = <16>;
423444
#dma-cells = <2>;
424-
dma-buf-addr-alignment = <4>;
425445
status = "disabled";
426446
};
427447

‎dts/arm/renesas/rz/rzn/r9a07g084.dtsi‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1144,5 +1144,43 @@
11441144
status = "disabled";
11451145
};
11461146
};
1147+
1148+
dma0: dma@80080000 {
1149+
compatible = "renesas,rz-dmac";
1150+
reg = <0x80080000 0x1000>;
1151+
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1152+
<GIC_SPI 22 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1153+
<GIC_SPI 23 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1154+
<GIC_SPI 24 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1155+
<GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1156+
<GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1157+
<GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1158+
<GIC_SPI 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1159+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
1160+
"ch4", "ch5", "ch6", "ch7";
1161+
dma-unit = <0>;
1162+
dma-channels = <8>;
1163+
#dma-cells = <2>;
1164+
status = "disabled";
1165+
};
1166+
1167+
dma1: dma@80081000 {
1168+
compatible = "renesas,rz-dmac";
1169+
reg = <0x80081000 0x1000>;
1170+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1171+
<GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1172+
<GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1173+
<GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1174+
<GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1175+
<GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1176+
<GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1177+
<GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1178+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
1179+
"ch4", "ch5", "ch6", "ch7";
1180+
dma-unit = <1>;
1181+
dma-channels = <8>;
1182+
#dma-cells = <2>;
1183+
status = "disabled";
1184+
};
11471185
};
11481186
};

‎dts/arm/renesas/rz/rzt/r9a07g075.dtsi‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1143,5 +1143,63 @@
11431143
status = "disabled";
11441144
};
11451145
};
1146+
1147+
dma0: dma@80080000 {
1148+
compatible = "renesas,rz-dmac";
1149+
reg = <0x80080000 0x1000>;
1150+
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1151+
<GIC_SPI 22 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1152+
<GIC_SPI 23 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1153+
<GIC_SPI 24 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1154+
<GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1155+
<GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1156+
<GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1157+
<GIC_SPI 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1158+
<GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1159+
<GIC_SPI 30 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1160+
<GIC_SPI 31 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1161+
<GIC_SPI 32 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1162+
<GIC_SPI 33 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1163+
<GIC_SPI 34 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1164+
<GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1165+
<GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1166+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
1167+
"ch4", "ch5", "ch6", "ch7",
1168+
"ch8", "ch9", "ch10", "ch11",
1169+
"ch12", "ch13", "ch14", "ch15";
1170+
dma-unit = <0>;
1171+
dma-channels = <16>;
1172+
#dma-cells = <2>;
1173+
status = "disabled";
1174+
};
1175+
1176+
dma1: dma@80081000 {
1177+
compatible = "renesas,rz-dmac";
1178+
reg = <0x80081000 0x1000>;
1179+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1180+
<GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1181+
<GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1182+
<GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1183+
<GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1184+
<GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1185+
<GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1186+
<GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1187+
<GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1188+
<GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1189+
<GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1190+
<GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1191+
<GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1192+
<GIC_SPI 50 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1193+
<GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1194+
<GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1195+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
1196+
"ch4", "ch5", "ch6", "ch7",
1197+
"ch8", "ch9", "ch10", "ch11",
1198+
"ch12", "ch13", "ch14", "ch15";
1199+
dma-unit = <1>;
1200+
dma-channels = <16>;
1201+
#dma-cells = <2>;
1202+
status = "disabled";
1203+
};
11461204
};
11471205
};

‎dts/arm/renesas/rz/rzv/r9a07g054.dtsi‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -925,6 +925,46 @@
925925
status = "disabled";
926926
};
927927
};
928+
929+
dma0: dma@41800000 { /* Secure DMA */
930+
compatible = "renesas,rz-dmac-b";
931+
reg = <0x41800000 0x800>, <0x41810000 0x20>;
932+
reg-names = "reg_main", "ext";
933+
interrupts = <108 1>, <109 1>, <110 1>, <111 1>,
934+
<112 1>, <113 1>, <114 1>, <115 1>,
935+
<116 1>, <117 1>, <118 1>, <119 1>,
936+
<120 1>, <121 1>, <122 1>, <123 1>,
937+
<124 1>; /* DMAERR */
938+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
939+
"ch4", "ch5", "ch6", "ch7",
940+
"ch8", "ch9", "ch10", "ch11",
941+
"ch12", "ch13", "ch14", "ch15",
942+
"err1";
943+
dma-unit = <0>;
944+
dma-channels = <16>;
945+
#dma-cells = <2>;
946+
status = "disabled";
947+
};
948+
949+
dma1: dma@41820000 { /* Secure DMA */
950+
compatible = "renesas,rz-dmac-b";
951+
reg = <0x41820000 0x800>, <0x41830000 0x20>;
952+
reg-names = "reg_main", "ext";
953+
interrupts = <125 1>, <126 1>, <127 1>, <128 1>,
954+
<129 1>, <130 1>, <131 1>, <132 1>,
955+
<133 1>, <134 1>, <135 1>, <136 1>,
956+
<137 1>, <138 1>, <139 1>, <140 1>,
957+
<141 1>; /* DMAERR */
958+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
959+
"ch4", "ch5", "ch6", "ch7",
960+
"ch8", "ch9", "ch10", "ch11",
961+
"ch12", "ch13", "ch14", "ch15",
962+
"err1";
963+
dma-unit = <1>;
964+
dma-channels = <16>;
965+
#dma-cells = <2>;
966+
status = "disabled";
967+
};
928968
};
929969
};
930970

‎dts/arm64/renesas/rz/rza/r9a07g063.dtsi‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -688,5 +688,36 @@
688688
status = "disabled";
689689
};
690690
};
691+
692+
dma0: dma@11820000 {
693+
compatible = "renesas,rz-dmac";
694+
reg = <0x11820000 0x800>, <0x11830000 0x20>;
695+
reg-names = "reg_main", "ext";
696+
interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
697+
<GIC_SPI 126 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
698+
<GIC_SPI 127 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
699+
<GIC_SPI 128 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
700+
<GIC_SPI 129 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
701+
<GIC_SPI 130 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
702+
<GIC_SPI 131 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
703+
<GIC_SPI 132 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
704+
<GIC_SPI 133 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
705+
<GIC_SPI 134 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
706+
<GIC_SPI 135 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
707+
<GIC_SPI 136 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
708+
<GIC_SPI 137 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
709+
<GIC_SPI 138 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
710+
<GIC_SPI 139 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
711+
<GIC_SPI 140 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
712+
<GIC_SPI 141 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
713+
interrupt-names = "ch0", "ch1", "ch2", "ch3",
714+
"ch4", "ch5", "ch6", "ch7",
715+
"ch8", "ch9", "ch10", "ch11",
716+
"ch12", "ch13", "ch14", "ch15",
717+
"err1";
718+
dma-channels = <16>;
719+
#dma-cells = <2>;
720+
status = "disabled";
721+
};
691722
};
692723
};

0 commit comments

Comments
 (0)