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Bradley Bolen
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soc: arm: xilinx_zynqmp: Add qemu based SoC
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <[email protected]>
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‎CODEOWNERS‎

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/dts/riscv/riscv32-fe310.dtsi @nategraff-sifive
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/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
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/dts/arm/armv7-r.dtsi @bbolen
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/dts/arm/xilinx/ @bbolen
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/dts/xtensa/xtensa.dtsi @ydamigos
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/dts/bindings/ @galak
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/dts/bindings/can/ @alexanderwachter

‎dts/arm/xilinx/zynqmp.dtsi‎

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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <mem.h>
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#include <arm/armv7-r.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic";
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reg = <0xf9010000 0x1000>,
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<0xf9020000 0x100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&core_intc 0>;
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label = "GIC";
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status = "okay";
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};
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flash0: flash@c0000000 {
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compatible = "soc-nv-flash";
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reg = <0xc0000000 DT_SIZE_K(64)>;
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = <0 DT_SIZE_K(256)>;
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};
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uart0: uart@ff000000 {
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compatible = "xlnx,xuartps";
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reg = <0xff000000 0x4c>;
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status = "disabled";
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interrupts = <21 0 IRQ_TYPE_LEVEL>;
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interrupt-names = "irq_0";
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label = "UART_0";
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};
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ttc0: timer@ff110000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupts = <36 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<37 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<38 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff110000 0x1000>;
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label = "ttc0";
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};
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ttc1: timer@ff120000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupts = <39 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<40 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<41 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff120000 0x1000>;
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label = "ttc1";
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};
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ttc2: timer@ff130000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupts = <42 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<43 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<44 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff130000 0x1000>;
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label = "ttc2";
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};
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ttc3: timer@ff140000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupts = <45 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<46 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>,
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<47 IRQ_DEFAULT_PRIORITY IRQ_TYPE_LEVEL>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff140000 0x1000>;
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label = "ttc3";
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};
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};
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};

‎soc/arm/xilinx_zynqmp/CMakeLists.txt‎

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# Copyright (c) 2019 Lexmark International, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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)

‎soc/arm/xilinx_zynqmp/Kconfig.defconfig‎

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# Copyright (c) 2019 Lexmark International, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_XILINX_ZYNQMP
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config SOC
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default "xilinx_zynqmp"
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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# - include the UART interrupts
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default 220
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config 2ND_LVL_ISR_TBL_OFFSET
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default 1
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config MAX_IRQ_PER_AGGREGATOR
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default 219
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config NUM_2ND_LEVEL_AGGREGATORS
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default 1
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 12000000
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config FLASH_SIZE
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default $(dt_int_val,DT_FLASH_SIZE)
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config FLASH_BASE_ADDRESS
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default $(dt_hex_val,DT_FLASH_BASE_ADDRESS)
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endif

‎soc/arm/xilinx_zynqmp/Kconfig.soc‎

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# Copyright (c) 2019 Lexmark International, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_XILINX_ZYNQMP
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bool "Xilinx ZynqMP"
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select CPU_CORTEX_R5
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select GIC
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select MULTI_LEVEL_INTERRUPTS
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select 2ND_LEVEL_INTERRUPTS

‎soc/arm/xilinx_zynqmp/dts_fixup.h‎

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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#undef DT_INST_0_XLNX_XUARTPS_IRQ_0
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#define DT_INST_0_XLNX_XUARTPS_IRQ_0 ((DT_INST_0_XLNX_XUARTPS_IRQ_IRQ_0 + 1) << 8)
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#undef DT_INST_0_CDNS_TTC_IRQ_0
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#define DT_INST_0_CDNS_TTC_IRQ_0 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_0 + 1) << 8)
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#undef DT_INST_0_CDNS_TTC_IRQ_1
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#define DT_INST_0_CDNS_TTC_IRQ_1 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_1 + 1) << 8)
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#undef DT_INST_0_CDNS_TTC_IRQ_2
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#define DT_INST_0_CDNS_TTC_IRQ_2 ((DT_INST_0_CDNS_TTC_IRQ_IRQ_2 + 1) << 8)

‎soc/arm/xilinx_zynqmp/linker.ld‎

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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <arch/arm/cortex_r/scripts/linker.ld>

‎soc/arm/xilinx_zynqmp/soc.c‎

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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <arch/cpu.h>
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* @return 0
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*/
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static int soc_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

‎soc/arm/xilinx_zynqmp/soc.h‎

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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include <device.h>
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#include <misc/util.h>
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _BOARD__H_ */

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