include: dt-bindings: stm32f4_clock.h: Add DCKCFGR registers

Add f4 binding files to provide DCKCFGR registers description
to enable clock selection for F410/F427/F446 variant lines

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

dts/arm/st/f4/stm32f410.dtsi

@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
 #include <st/f4/stm32f4.dtsi>
 
 / {

dts/arm/st/f4/stm32f427.dtsi

@@ -5,6 +5,7 @@
  */
 
 #include <st/f4/stm32f407.dtsi>
+#include <zephyr/dt-bindings/clock/stm32f427_clock.h>
 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
 
 / {

dts/arm/st/f4/stm32f437.dtsi

@@ -5,6 +5,7 @@
  */
 
 #include <st/f4/stm32f407.dtsi>
+#include <zephyr/dt-bindings/clock/stm32f427_clock.h>
 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
 
 / {

dts/arm/st/f4/stm32f446.dtsi

@@ -5,6 +5,7 @@
  */
 
 #include <st/f4/stm32f401.dtsi>
+#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
 
 / {

include/zephyr/dt-bindings/clock/stm32f410_clock.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2023 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
+
+/** @brief RCC_DCKCFGR register offset */
+#define DCKCFGR_REG		0x8C
+#define DCKCFGR2_REG		0x94
+
+/** @brief Device domain clocks selection helpers */
+/** DCKCFGR devices */
+#define CKDFSDM2A_SEL(val)	STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
+#define CKDFSDM1A_SEL(val)	STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
+#define SAI1A_SEL(val)		STM32_CLOCK(val, 2, 20, DCKCFGR_REG)
+#define SAI1B_SEL(val)		STM32_CLOCK(val, 2, 22, DCKCFGR_REG)
+#define I2S1_SEL(val)		STM32_CLOCK(val, 2, 25, DCKCFGR_REG)
+#define I2S2_SEL(val)		STM32_CLOCK(val, 2, 27, DCKCFGR_REG)
+#define CKDFSDM_SEL(val)	STM32_CLOCK(val, 1, 31, DCKCFGR_REG)
+
+/** DCKCFGR2 devices */
+#define I2CFMP1_SEL(val)	STM32_CLOCK(val, 1, 22, DCKCFGR2_REG)
+#define CK48M_SEL(val)		STM32_CLOCK(val, 1, 27, DCKCFGR2_REG)
+#define SDIO_SEL(val)		STM32_CLOCK(val, 1, 28, DCKCFGR2_REG)
+#define LPTIM1_SEL(val)		STM32_CLOCK(val, 1, 30, DCKCFGR2_REG)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f427_clock.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
+
+/** @brief RCC_DCKCFGR register offset */
+#define DCKCFGR_REG		0x8C
+
+/** @brief Device domain clocks selection helpers */
+/** DCKCFGR devices */
+#define CKDFSDM2A_SEL(val)	STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
+#define CKDFSDM1A_SEL(val)	STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
+#define SAI1A_SEL(val)		STM32_CLOCK(val, 2, 20, DCKCFGR_REG)
+#define SAI1B_SEL(val)		STM32_CLOCK(val, 2, 22, DCKCFGR_REG)
+#define CLK48M_SEL(val)		STM32_CLOCK(val, 1, 27, DCKCFGR_REG)
+#define SDMMC_SEL(val)		STM32_CLOCK(val, 1, 28, DCKCFGR_REG)
+#define DSI_SEL(val)		STM32_CLOCK(val, 1, 29, DCKCFGR_REG)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */