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Johan Hedbergjhedberg
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boards: x86: Add ehl_crb board definition
Add initial definition for the Elkhart Lake CRB board. Signed-off-by: Johan Hedberg <[email protected]>
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boards/x86/ehl_crb/CMakeLists.txt

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# Create an EFI image
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if(CONFIG_BOARD_EHL_CRB)
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
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-f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
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$<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
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WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
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)
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endif()

boards/x86/ehl_crb/Kconfig.board

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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_EHL_CRB
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bool "Elkhart Lake CRB"
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depends on SOC_ELKHART_LAKE
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select X86_64
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_EHL_CRB
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config BOARD
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default "ehl_crb"
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config BUILD_OUTPUT_STRIPPED
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default y
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config MP_NUM_CPUS
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default 2
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config X86_MMU_PAGE_POOL_PAGES
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default 3072 if X86_MMU
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endif # BOARD_EHL_CRB

boards/x86/ehl_crb/board.cmake

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# SPDX-License-Identifier: Apache-2.0
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board_set_flasher_ifnset(misc-flasher)
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board_finalize_runner_args(misc-flasher)

boards/x86/ehl_crb/ehl_crb.dts

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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#define DT_DRAM_SIZE DT_SIZE_M(2048)
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#include <elkhart_lake.dtsi>
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/ {
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model = "ehl_crb";
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compatible = "intel,elkhart_lake";
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chosen {
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zephyr,sram = &dram0;
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zephyr,console = &uart2;
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zephyr,shell-uart = &uart2;
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zephyr,bt-uart = &uart1;
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zephyr,uart-pipe = &uart1;
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zephyr,bt-mon-uart = &uart1;
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};
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};

boards/x86/ehl_crb/ehl_crb.yaml

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identifier: ehl_crb
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name: Elkhart Lake CRB
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type: mcu
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arch: x86
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toolchain:
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- zephyr
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ram: 2048
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testing:
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ignore_tags:
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- net
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- bluetooth
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_ELKHART_LAKE=y
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CONFIG_BOARD_EHL_CRB=y
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_CONSOLE=y
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CONFIG_X2APIC=y
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CONFIG_SMP=y
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CONFIG_X86_MMU_PAGE_POOL_PAGES=3092

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