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boards: openhwgroup: add CVA6 Testbench
Adds support for the CVA6 CPU in the hardware simulation / testbench environment. Especially, configurations are added that allow the application to indicate success or error to the testbench. The SoC currently contains the CVA CPU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, a GPIO and the lowRISC ethernet subsystem (which is currently without a driver in zephyr). Two sample applications are provided, demonstrating how to indicate success or failure to the testbench. Signed-off-by: Eric Ackermann <[email protected]>
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‎boards/openhwgroup/cv32a6_testbench/Kconfig.cv32a6_testbench‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV32A6_TESTBENCH
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select SOC_CV32A6
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select SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF

‎boards/openhwgroup/cv32a6_testbench/board.yml‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv32a6_testbench
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vendor: openhwgroup
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socs:
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- name: cv32a6

‎boards/openhwgroup/cv32a6_testbench/cv32a6_testbench.dts‎

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/*
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* Copyright(c) 2024, CISPA Helmholtz Center for Information Security
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv32a6.dtsi>
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/ {
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model = "CVA6 CPU in testbench";
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compatible = "ariane,cv32a6_testbench";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&clint{
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status = "okay";
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};
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&dma0 {
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status = "disabled";
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};
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&mdio0{
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status = "disabled";
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};
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&eth0 {
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status = "disabled";
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};

‎boards/openhwgroup/cv32a6_testbench/cv32a6_testbench_defconfig‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_BASE64=y
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
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CONFIG_CONSOLE_HANDLER=y
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CONFIG_XIP=n
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CONFIG_INIT_STACKS=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
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CONFIG_FPU=y
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CONFIG_POWEROFF=y
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# RNG
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CONFIG_TIMER_RANDOM_GENERATOR=y
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CONFIG_TEST_RANDOM_GENERATOR=y
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# IRQs
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CONFIG_MULTI_LEVEL_INTERRUPTS=y
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CONFIG_2ND_LEVEL_INTERRUPTS=y
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# 1 PLIC
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
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CONFIG_PLIC=y
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CONFIG_3RD_LEVEL_INTERRUPTS=n
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# logging
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CONFIG_LOG=y
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# immediate is required so it is not lost on test failure
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CONFIG_LOG_MODE_IMMEDIATE=y
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CONFIG_LOG_DEFAULT_LEVEL=4
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CONFIG_THREAD_NAME=y
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CONFIG_ISR_STACK_SIZE=32768
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CONFIG_MAIN_STACK_SIZE=32768
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CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=32768
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CONFIG_IDLE_STACK_SIZE=32768

‎boards/openhwgroup/cv64a6_testbench/Kconfig.cv64a6_testbench‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV64A6_TESTBENCH
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select SOC_CV64A6_IMAFDC
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select SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF

‎boards/openhwgroup/cv64a6_testbench/board.yml‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv64a6_testbench
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vendor: openhwgroup
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socs:
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- name: cv64a6

‎boards/openhwgroup/cv64a6_testbench/cv64a6_testbench.dts‎

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/*
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* Copyright(c) 2024, CISPA Helmholtz Center for Information Security
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv64a6.dtsi>
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/ {
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model = "CVA6 CPU in testbench";
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compatible = "ariane,cv64a6_testbench";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&clint{
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status = "okay";
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};
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&dma0 {
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status = "disabled";
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};
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&mdio0{
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status = "disabled";
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};
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&eth0 {
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status = "disabled";
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};

‎boards/openhwgroup/cv64a6_testbench/cv64a6_testbench_defconfig‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_BASE64=y
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
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CONFIG_CONSOLE_HANDLER=y
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CONFIG_XIP=n
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CONFIG_INIT_STACKS=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
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CONFIG_FPU=y
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CONFIG_POWEROFF=y
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# RNG
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CONFIG_TIMER_RANDOM_GENERATOR=y
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CONFIG_TEST_RANDOM_GENERATOR=y
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# IRQs
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CONFIG_MULTI_LEVEL_INTERRUPTS=y
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CONFIG_2ND_LEVEL_INTERRUPTS=y
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# 1 PLIC
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
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CONFIG_PLIC=y
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CONFIG_3RD_LEVEL_INTERRUPTS=n
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# logging
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CONFIG_LOG=y
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# immediate is required so it is not lost on test failure
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CONFIG_LOG_MODE_IMMEDIATE=y
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CONFIG_LOG_DEFAULT_LEVEL=4
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CONFIG_THREAD_NAME=y
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CONFIG_ISR_STACK_SIZE=32768
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CONFIG_MAIN_STACK_SIZE=32768
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CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=32768
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CONFIG_IDLE_STACK_SIZE=32768

‎samples/boards/openhwgroup/sim_fail/CMakeLists.txt‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(cv64a6_sim_fail)
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target_sources(app PRIVATE src/main.c)

‎samples/boards/openhwgroup/sim_fail/README.rst‎

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.. _hello_world:
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Failing test
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###########
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Overview
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********
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A simple sample that can be used in the cv64a6 simulator.
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Prints "Test failure" to the console and indicates failure to the testbench.
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Building and Running
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********************
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This application can be built and executed in the cv64a6 testbench as follows:
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.. code-block:: console
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west build -p always -b cv64a6_testbench samples/boards/openhwgroup/cva6/sim_fail/
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ln -s $(pwd)/build/zephyr/zephyr.elf build/zephyr/zephyr.o
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python3 $CVA6_ROOT/verif/sim/cva6.py --elf_tests $ZEPHYR_ROOT/build/zephyr/zephyr.o --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=veri-testharness --spike_params="/top/max_steps_enabled=y" $DV_OPTS
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To build for another board, change "cv64a6_testbench" above to that board's name.
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Sample Output
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=============
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.. code-block:: console
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Test Failure x86
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Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.

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