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drivers: gpio: gpio driver
Add gpio driver for ENE KB106X Signed-off-by: Steven Chang <[email protected]>
1 parent d9310b6 commit 7d2be3b

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‎drivers/gpio/CMakeLists.txt

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@@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_DAVINCI gpio_davinci.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_DW gpio_dw.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_EFINIX_SAPPHIRE gpio_efinix_sapphire.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_EMUL gpio_emul.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ENE_KB106X gpio_ene_kb106x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ENE_KB1200 gpio_ene_kb1200.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_EOS_S3 gpio_eos_s3.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ESP32 gpio_esp32.c)

‎drivers/gpio/Kconfig.ene

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@@ -7,3 +7,10 @@ config GPIO_ENE_KB1200
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depends on DT_HAS_ENE_KB1200_GPIO_ENABLED
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help
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Enable support for the kb1200 GPIO controllers.
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config GPIO_ENE_KB106X
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bool "ENE KB106X GPIO Driver"
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default y
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depends on DT_HAS_ENE_KB106X_GPIO_ENABLED
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help
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Enable support for the KB106X GPIO controllers.

‎drivers/gpio/gpio_ene_kb106x.c

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ene_kb106x_gpio
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/dt-bindings/gpio/ene-kb106x-gpio.h>
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#include <zephyr/sys/util_macro.h>
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#include <reg/gpio.h>
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#include <reg/gptd.h>
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struct gpio_kb106x_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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struct gpio_kb106x_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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/* base address of GPIO port */
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struct gpio_regs *gpio_regs;
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struct gptd_regs *gptd_regs;
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};
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static void gpio_kb106x_isr(const struct device *dev)
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{
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const struct gpio_kb106x_config *config = dev->config;
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struct gpio_kb106x_data *context = dev->data;
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uint32_t pending_flag = config->gptd_regs->GPTDPF;
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gpio_fire_callbacks(&context->cb, dev, pending_flag);
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config->gptd_regs->GPTDPF = pending_flag;
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}
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static int kb106x_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_kb106x_config *config = dev->config;
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/* ene specific flags. low voltage mode, input voltage threshold (ViH & ViL) 1.8V */
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if (flags & ENE_GPIO_VOLTAGE_1P8) {
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WRITE_BIT(config->gpio_regs->GPIOLV, pin, 1);
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} else {
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WRITE_BIT(config->gpio_regs->GPIOLV, pin, 0);
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}
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/* ene specific flags. max current driving ability, max support 16 mA */
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if (flags & ENE_GPIO_DRIVING_16MA) {
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WRITE_BIT(config->gpio_regs->GPIODC, pin, 1);
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} else {
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WRITE_BIT(config->gpio_regs->GPIODC, pin, 0);
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}
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/* pull-up function */
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if (flags & GPIO_PULL_UP) {
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WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1);
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} else {
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WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0);
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}
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/* output data high/low */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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WRITE_BIT(config->gpio_regs->GPIOD, pin, 1);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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WRITE_BIT(config->gpio_regs->GPIOD, pin, 0);
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}
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/* output enable function */
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if (flags & GPIO_OUTPUT) {
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/* [patch] setting open-drain only when output is enabled */
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/* output type push-pull/open-drain */
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if (flags & GPIO_SINGLE_ENDED) {
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if (flags & GPIO_LINE_OPEN_DRAIN) {
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WRITE_BIT(config->gpio_regs->GPIOOD, pin, 1);
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} else {
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WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
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}
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} else {
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WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
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}
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WRITE_BIT(config->gpio_regs->GPIOOE, pin, 1);
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} else {
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WRITE_BIT(config->gpio_regs->GPIOOE, pin, 0);
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/* [patch] disable open-drain when output is disabled */
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WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
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}
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/* input enable function */
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if (flags & GPIO_INPUT) {
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WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1);
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} else {
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WRITE_BIT(config->gpio_regs->GPIOIE, pin, 0);
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}
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return 0;
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}
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static int kb106x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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const struct gpio_kb106x_config *config = dev->config;
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*value = config->gpio_regs->GPIOIN;
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return 0;
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}
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static int kb106x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_kb106x_config *config = dev->config;
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config->gpio_regs->GPIOD |= (value & mask);
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return 0;
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}
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static int kb106x_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_kb106x_config *config = dev->config;
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config->gpio_regs->GPIOD |= pins;
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return 0;
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}
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static int kb106x_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_kb106x_config *config = dev->config;
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config->gpio_regs->GPIOD &= ~pins;
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return 0;
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}
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static int kb106x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct gpio_kb106x_config *config = dev->config;
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config->gpio_regs->GPIOD ^= pins;
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return 0;
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}
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static int kb106x_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_kb106x_config *config = dev->config;
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if (mode & GPIO_INT_EDGE) {
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WRITE_BIT(config->gptd_regs->GPTDEL, pin, 0);
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if (trig & GPIO_INT_HIGH_1) {
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if (trig & GPIO_INT_LOW_0) { /* Falling & Rising edge trigger */
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/* Enable toggle trigger */
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WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 1);
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} else { /* Rising edge */
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/* Disable toggle trigger */
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WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0);
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WRITE_BIT(config->gptd_regs->GPTDPS, pin, 1);
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}
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} else { /* Falling edge */
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/* Disable Toggle trigger */
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WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0);
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WRITE_BIT(config->gptd_regs->GPTDPS, pin, 0);
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}
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} else {
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WRITE_BIT(config->gptd_regs->GPTDEL, pin, 1);
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/* Disable Toggle trigger */
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WRITE_BIT(config->gptd_regs->GPTDCHG, pin, 0);
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if (trig & GPIO_INT_HIGH_1) {
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WRITE_BIT(config->gptd_regs->GPTDPS, pin, 1);
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} else {
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WRITE_BIT(config->gptd_regs->GPTDPS, pin, 0);
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}
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}
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/* clear pending flag */
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WRITE_BIT(config->gptd_regs->GPTDPF, pin, 1);
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/* Check if GPIO port needs interrupt support */
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if ((mode & GPIO_INT_DISABLE) || (mode & GPIO_INT_ENABLE) == 0) {
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/* Set the mask to disable the interrupt */
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WRITE_BIT(config->gptd_regs->GPTDIE, pin, 0);
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} else {
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/* Enable the interrupt */
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WRITE_BIT(config->gptd_regs->GPTDIE, pin, 1);
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}
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/* Check GPIO wakeup enable */
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if (trig & GPIO_INT_TRIG_WAKE) {
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WRITE_BIT(config->gptd_regs->GPTDWE, pin, 1);
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} else {
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WRITE_BIT(config->gptd_regs->GPTDWE, pin, 0);
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}
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return 0;
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}
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static int kb106x_gpio_manage_callback(const struct device *dev, struct gpio_callback *cb, bool set)
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{
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struct gpio_kb106x_data *context = dev->data;
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gpio_manage_callback(&context->cb, cb, set);
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return 0;
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}
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static uint32_t kb106x_gpio_get_pending_int(const struct device *dev)
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{
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const struct gpio_kb106x_config *const config = dev->config;
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return config->gptd_regs->GPTDPF;
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}
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static const struct gpio_driver_api kb106x_gpio_api = {
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.pin_configure = kb106x_gpio_pin_configure,
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.port_get_raw = kb106x_gpio_port_get_raw,
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.port_set_masked_raw = kb106x_gpio_port_set_masked_raw,
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.port_set_bits_raw = kb106x_gpio_port_set_bits_raw,
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.port_clear_bits_raw = kb106x_gpio_port_clear_bits_raw,
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.port_toggle_bits = kb106x_gpio_port_toggle_bits,
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.pin_interrupt_configure = kb106x_gpio_pin_interrupt_configure,
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.manage_callback = kb106x_gpio_manage_callback,
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.get_pending_int = kb106x_gpio_get_pending_int,
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};
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#define KB106X_GPIO_INIT(n) \
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static int kb106x_gpio_##n##_init(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), DT_INST_IRQ_BY_IDX(n, 0, priority), \
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gpio_kb106x_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), DT_INST_IRQ_BY_IDX(n, 1, priority), \
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gpio_kb106x_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
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return 0; \
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}; \
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static const struct gpio_kb106x_config port_##n##_kb106x_config = { \
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.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n)}, \
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.gpio_regs = (struct gpio_regs *)DT_INST_REG_ADDR_BY_IDX(n, 0), \
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.gptd_regs = (struct gptd_regs *)DT_INST_REG_ADDR_BY_IDX(n, 1), \
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}; \
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static struct gpio_kb106x_data gpio_kb106x_##n##_data; \
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DEVICE_DT_INST_DEFINE(n, &kb106x_gpio_##n##_init, NULL, &gpio_kb106x_##n##_data, \
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&port_##n##_kb106x_config, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&kb106x_gpio_api);
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DT_INST_FOREACH_STATUS_OKAY(KB106X_GPIO_INIT)

‎dts/arm/ene/kb106x/kb106x.dtsi

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#size-cells = <1>;
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reg = <0x50000000 0x100>;
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status = "okay";
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gpio0x1x: gpio@50000000 {
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compatible = "ene,kb106x-gpio";
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reg = <0x50000000 0x04>, <0x50010000 0x04>;
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interrupts = <2 3>, <3 3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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gpio2x3x: gpio@50000004 {
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compatible = "ene,kb106x-gpio";
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reg = <0x50000004 0x04>, <0x50010004 0x04>;
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interrupts = <4 3>, <5 3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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gpio4x5x: gpio@50000008 {
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compatible = "ene,kb106x-gpio";
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reg = <0x50000008 0x04>, <0x50010008 0x04>;
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interrupts = <6 3>, <7 3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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gpio6x7x: gpio@5000000c {
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compatible = "ene,kb106x-gpio";
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reg = <0x5000000C 0x04>, <0x5001000C 0x04>;
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interrupts = <8 3>, <9 3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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egpio0x1x: gpio@50000100 {
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compatible = "ene,kb106x-gpio";
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reg = <0x50000100 0x04>, <0x50010100 0x04>;
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interrupts = <2 3>, <3 3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "disabled";
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};
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};
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};
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};

‎dts/bindings/gpio/ene,kb106x-gpio.yaml

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# Copyright (c) 2025 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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ENE KB106X GPIO(General purpose IO) Port node
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The GPIO controller provides group control of GPIO functions. Each port
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group contains 32 pins. GPIO_00~GPIO_1F belong to the Port0 group,
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GPIO_20~GPIO_3F belong to the Port1 group, and so on.
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In particular, the 32 pins of the port group do not share the same IRQ
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interrupt, but are assigned to two different IRQ interrupts in groups of 16
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pins. This means that single port group provide two interrupt source.
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ex.Port0 group GPIO_00~GPIO_0F shares IRQ18, and Port0 group
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GPIO_10~GPIO_1F shares IRQ19.
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compatible: "ene,kb106x-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

‎include/zephyr/dt-bindings/gpio/ene-kb106x-gpio.h

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB106X_GPIO_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB106X_GPIO_H_
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/**
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* @name GPIO pin voltage flags
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*
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* The voltage flags are a Zephyr specific extension of the standard GPIO flags
13+
* specified by the Linux GPIO binding for use with the ENE KB106x SoCs.
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*
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* @{
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* Note: Bits 15 down to 8 are reserved for SoC specific flags.
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*/
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/** @cond INTERNAL_HIDDEN */
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#define ENE_GPIO_VOLTAGE_POS 8
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#define ENE_GPIO_VOLTAGE_MASK (1U << ENE_GPIO_VOLTAGE_POS)
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#define ENE_GPIO_DRIVING_POS 9
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#define ENE_GPIO_DRIVING_MASK (1U << ENE_GPIO_DRIVING_POS)
25+
/** @endcond */
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/** Set pin at the default voltage level (3.3V) */
28+
#define ENE_GPIO_VOLTAGE_DEFAULT (0U << ENE_GPIO_VOLTAGE_POS)
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/** Set pin voltage level at 1.8 V */
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#define ENE_GPIO_VOLTAGE_1P8 (1U << ENE_GPIO_VOLTAGE_POS)
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/** Set pin at the default driving current (4mA) */
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#define ENE_GPIO_DRIVING_DEFAULT (0U << ENE_GPIO_DRIVING_POS)
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/** Set pin driving current at 16mA */
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#define ENE_GPIO_DRIVING_16MA (1U << ENE_GPIO_DRIVING_POS)
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/** @} */
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB106X_GPIO_H_ */

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