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boards: esp32s3_devkitm: initial soc board support
Adds support to ESP32-S3 devkitm as initial SoC board. Signed-off-by: Sylvio Alves <[email protected]>
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‎boards/xtensa/esp32s3_devkitm/Kconfig.board‎

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# ESP32S3 DevKitM board configuration
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# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_ESP32S3_DEVKITM
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bool "ESP32S3 DevKitM Board"
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depends on SOC_ESP32S3

‎boards/xtensa/esp32s3_devkitm/Kconfig.defconfig‎

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# ESP32S3 DevKitM board configuration
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# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config BOARD
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default "esp32s3_devkitm"
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depends on BOARD_ESP32S3_DEVKITM

‎boards/xtensa/esp32s3_devkitm/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
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set(OPENOCD OPENOCD-NOTFOUND)
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endif()
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find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
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include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/xtensa/esp32s3_devkitm/doc/index.rst‎

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.. _esp32s3_devkitm:
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ESP32S3-DevKitM
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###############
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Overview
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********
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The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1
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or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi
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and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_
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Hardware
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********
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ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
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and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
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(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
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RF module, and numerous peripherals.
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ESP32-S3 DevKitM includes the following features:
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- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
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- Additional vector instructions support for AI acceleration
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- 512KB of SRAM
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- 384KB of ROM
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- Wi-Fi 802.11b/g/n
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- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate
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Digital interfaces:
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- 45 programmable GPIOs
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- 4x SPI
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- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411
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- 1x DVP 8-bit ~16-bit camera interface
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- 3x UART
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- 2x I2C
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- 2x I2S
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- 1x RMT (TX/RX)
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- 1x pulse counter
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- LED PWM controller, up to 8 channels
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- 1x full-speed USB OTG
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- 1x USB Serial/JTAG controller
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- 2x MCPWM
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- 1x SDIO host controller with 2 slots
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- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels
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- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)
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- Addressable RGB LED, driven by GPIO48.
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Analog interfaces:
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- 2x 12-bit SAR ADCs, up to 20 channels
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- 1x temperature sensor
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- 14x touch sensing IOs
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Timers:
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- 4x 54-bit general-purpose timers
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- 1x 52-bit system timer
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- 3x watchdog timers
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Low Power:
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- Power Management Unit with five power modes
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- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM
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Security:
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- Secure boot
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- Flash encryption
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- 4-Kbit OTP, up to 1792 bits for users
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- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature)
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For more information, check the datasheet at `ESP32-S3 Datasheet`_.
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Supported Features
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==================
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Current Zephyr's ESP32-S3-DevKitM board supports the following features:
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+------------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+============+============+=====================================+
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+------------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+------------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+------------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+------------+------------+-------------------------------------+
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| USB-JTAG | on-chip | hardware interface |
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+------------+------------+-------------------------------------+
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Prerequisites
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-------------
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Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
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below to retrieve those files.
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.. code-block:: console
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west blobs fetch hal_espressif
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.. note::
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It is recommended running the command above after :file:`west update`.
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Building & Flashing
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-------------------
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Build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32s3_devkitm
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:goals: build
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The usual ``flash`` target will work with the ``esp32s3_devkitm`` board
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configuration. Here is an example for the :ref:`hello_world`
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application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32s3_devkitm
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:goals: flash
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Open the serial monitor using the following command:
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.. code-block:: shell
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west espressif monitor
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After the board has automatically reset and booted, you should see the following
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message in the monitor:
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.. code-block:: console
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***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
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Hello World! esp32s3_devkitm
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Debugging
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---------
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As with much custom hardware, the ESP32 modules require patches to
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OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
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the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
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The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
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``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
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parameter when building.
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Here is an example for building the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32s3_devkitm
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:goals: build flash
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:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
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You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: esp32s3_devkitm
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:goals: debug
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References
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**********
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.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html
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.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf
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.. _`ESP32 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
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.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
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.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases

‎boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi‎

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/*
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
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#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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pinmux = <UART0_TX_GPIO43>;
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};
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group2 {
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pinmux = <UART0_RX_GPIO44>;
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bias-pull-up;
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};
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};
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};

‎boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts‎

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/*
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <espressif/esp32s3.dtsi>
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#include "esp32s3_devkitm-pinctrl.dtsi"
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/ {
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model = "esp32s3_devkitm";
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compatible = "espressif,esp32s3";
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chosen {
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zephyr,sram = &sram0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,flash = &flash0;
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};
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aliases {
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uart-0 = &uart0;
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sw0 = &button0;
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "BOOT Button";
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};
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};
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};
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&cpu0 {
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clock-frequency = <ESP32_CLK_CPU_240M>;
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};
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&cpu1 {
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clock-frequency = <ESP32_CLK_CPU_240M>;
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&uart0_default>;
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pinctrl-names = "default";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&flash0 {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Reserve 64kB for the bootloader */
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x00000000 0x00010000>;
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read-only;
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};
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/* Reserve 1024kB for the application in slot 0 */
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x00010000 0x00100000>;
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};
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/* Reserve 1024kB for the application in slot 1 */
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slot1_partition: partition@110000 {
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label = "image-1";
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reg = <0x00110000 0x00100000>;
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};
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/* Reserve 256kB for the scratch partition */
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scratch_partition: partition@210000 {
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label = "image-scratch";
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reg = <0x00210000 0x00040000>;
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};
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storage_partition: partition@250000 {
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label = "storage";
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reg = <0x00250000 0x00006000>;
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};
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};
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};

‎boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml‎

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identifier: esp32s3_devkitm
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name: ESP32-S3 DevKitM
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type: mcu
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arch: xtensa
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toolchain:
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- espressif
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supported:
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- gpio
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- uart
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testing:
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ignore_tags:
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- net
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- bluetooth

‎boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig‎

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XTENSA_RESET_VECTOR=n
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CONFIG_BOARD_ESP32S3_DEVKITM=y
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CONFIG_SOC_ESP32S3=y
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_XTENSA_USE_CORE_CRT1=n
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CONFIG_GPIO=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_CLOCK_CONTROL=y

‎boards/xtensa/esp32s3_devkitm/support/openocd.cfg‎

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set ESP_RTOS none
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set ESP32_ONLYCPU 1
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# Source the JTAG interface configuration file
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source [find interface/esp_usb_jtag.cfg]
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# Source the ESP32-S3 configuration file
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source [find target/esp32s3.cfg]

‎tests/lib/heap/testcase.yaml‎

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tests:
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libraries.heap:
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tags: heap
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platform_exclude: m2gl025_miv qemu_xtensa esp32s2_saola
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platform_exclude: m2gl025_miv qemu_xtensa esp32s2_saola esp32s3_devkitm
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filter: not CONFIG_SOC_NSIM
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timeout: 480

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