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boards: arc: add a nsim_hs_mpuv6 board simulator
We add support of mpu v6 therefore it is needed to have a board to validate that feature. This commit add a new HS nsim simulator which supports mpu v6. Signed-off-by: Yuguo Zou <[email protected]>
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‎boards/arc/nsim/nsim_hs_mpuv6.dts‎

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/*
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* Copyright (c) 2021, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include "nsim.dtsi"
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/ {
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model = "snps,nsim_hs";
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compatible = "snps,nsim_hs";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,archs";
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reg = <0>;
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};
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};
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};

‎boards/arc/nsim/nsim_hs_mpuv6.yaml‎

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identifier: nsim_hs_mpuv6
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name: HS (with MPU v6) nSIM simulator
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type: mcu
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simulation: nsim
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arch: arc
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toolchain:
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- zephyr
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- arcmwdt
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testing:
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default: true
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ignore_tags:
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- net
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- bluetooth

‎boards/arc/nsim/nsim_hs_mpuv6_defconfig‎

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_NSIM=y
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CONFIG_SOC_NSIM_HS_MPUV6=y
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CONFIG_BOARD_NSIM=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
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CONFIG_XIP=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_PRINTK=y
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CONFIG_ARCV2_INTERRUPT_UNIT=y
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CONFIG_ARCV2_TIMER=y
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CONFIG_ARC_MPU_ENABLE=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_ARC_EXCEPTION_DEBUG=y

‎boards/arc/nsim/support/mdb_hs_mpuv6.args‎

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-arcv2hs
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-core2
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-arcnum=3
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-rgf_num_banks=2
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-rgf_banked_regs=32
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-rgf_num_wr_ports=2
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-Xatomic
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-Xll64
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-Xunaligned
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-Xcode_density
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-Xdiv_rem=radix4
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-Xswap
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-Xbitscan
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-Xmpy_option=qmpyh
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-mpuv6
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-mpu_regions=32
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-Xshift_assist
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-Xbarrel_shifter
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-Xfpud_div
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-Xfpu_mac
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-Xtimer0
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-Xtimer0_level=1
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-Xtimer1
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-Xtimer1_level=0
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-Xrtc
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-action_points=8
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-Xstack_check
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-interrupts=72
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-interrupt_priorities=2
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-ext_interrupts=70
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-firq
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-interrupt_base=0x0
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-dcache=65536,64,2,a
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-dcache_feature=2
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-dcache_uncached_region
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-dcache_mem_cycles=2
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-icache=65536,64,4,a
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-icache_feature=2
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-dccm_size=0x40000
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-dccm_base=0x80000000
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-dccm_mem_cycles=2
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-iccm0_size=0x40000
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-iccm0_base=0x70000000
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-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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-noprofile

‎boards/arc/nsim/support/nsim_hs_mpuv6.props‎

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nsim_isa_family=av2hs
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nsim_isa_core=2
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arcver=0x52
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nsim_isa_rgf_num_banks=2
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nsim_isa_rgf_banked_regs=32
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nsim_isa_rgf_num_regs=32
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nsim_isa_rgf_num_wr_ports=2
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nsim_isa_big_endian=0
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nsim_isa_lpc_size=32
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nsim_isa_pc_size=32
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nsim_isa_addr_size=32
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nsim_isa_atomic_option=1
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nsim_isa_ll64_option=1
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nsim_isa_unaligned_option=1
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nsim_isa_code_density_option=2
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nsim_isa_div_rem_option=2
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nsim_isa_swap_option=1
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nsim_isa_bitscan_option=1
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nsim_isa_mpy_option=9
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nsim_isa_shift_option=3
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mpu_regions=32
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mpu_version=6
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nsim_isa_fpud_div_option=1
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nsim_isa_fpu_mac_option=1
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nsim_isa_enable_timer_0=1
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nsim_isa_timer_0_int_level=1
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nsim_isa_enable_timer_1=1
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nsim_isa_timer_1_int_level=0
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nsim_isa_rtc_option=1
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nsim_isa_num_actionpoints=8
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nsim_isa_stack_checking=1
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nsim_isa_number_of_interrupts=72
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nsim_isa_number_of_levels=2
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nsim_isa_number_of_external_interrupts=70
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nsim_isa_fast_irq=1
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nsim_isa_intvbase_preset=0x0
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dcache=65536,64,2,a
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nsim_isa_dc_feature_level=2
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nsim_isa_dc_uncached_region=1
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nsim_isa_dc_mem_cycles=2
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icache=65536,64,4,a
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nsim_isa_ic_feature_level=2
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dccm_size=0x40000
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dccm_base=0x80000000
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nsim_isa_dccm_mem_cycles=2
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iccm0_size=0x40000
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iccm0_base=0x70000000
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nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24

‎soc/arc/snps_nsim/CMakeLists.txt‎

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-Xtimer0 -Xtimer1)
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zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_SMP -Hlib=hs38_full)
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zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -arcv2hs -core2 -Xatomic
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-Xunaligned -Xcode_density -Xswap -Xbitscan
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-Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter
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-Xtimer0 -Xtimer1)
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zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)
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endif()
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zephyr_sources(

‎soc/arc/snps_nsim/Kconfig‎

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bool "Multi-core Synopsys ARC HS in nSIM"
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select CPU_HAS_FPU
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config SOC_NSIM_HS_MPUV6
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bool "Synopsys ARC HS with MPU v6 in nSIM"
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select CPU_HAS_MPU
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select CPU_HAS_FPU
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config SOC_NSIM_HS6X
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bool "Synopsys ARC HS6x in nSIM"
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‎soc/arc/snps_nsim/Kconfig.defconfig‎

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source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp"
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source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x"
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source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp"
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source "soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6"
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endif # SOC_NSIM

‎soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6‎

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# Copyright (c) 2021 Synopsys, Inc. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NSIM_HS_MPUV6
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config CPU_HS3X
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default y
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 16 priority levels:
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# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
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default 2
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 30
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config ARC_MPU_VER
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default 6
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config MAX_DOMAIN_PARTITIONS
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default 32 if USERSPACE
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config RGF_NUM_BANKS
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default 2
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 5000000
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config HARVARD
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default y
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config ARC_FIRQ
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default y
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config CACHE_MANAGEMENT
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default y
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endif # SOC_NSIM_HS_MPUV6

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