arch: arm: cortex_m: pm_s2ram: ignore xPSR

Remove all xPSR-related registers from struct __cpu_context, and the
associated save/restore code in S2RAM code, as they are not needed:

* EPSR and IPSR are read-only - they cannot be "restored"
* Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR
  could be restored, but this is not needed as the AAPCS indicates these
  bits to be "undefined on entry to or return from a public interface"

Signed-off-by: Mathieu Choplain <[email protected]>

Author: Mathieu Choplain

arch/arm/core/cortex_m/pm_s2ram.S

@@ -46,15 +46,6 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	mrs	r2, psplim
 	str	r2, [r1, #___cpu_context_t_psplim_OFFSET]
 
-	mrs	r2, apsr
-	str	r2, [r1, #___cpu_context_t_apsr_OFFSET]
-
-	mrs	r2, ipsr
-	str	r2, [r1, #___cpu_context_t_ipsr_OFFSET]
-
-	mrs	r2, epsr
-	str	r2, [r1, #___cpu_context_t_epsr_OFFSET]
-
 	mrs	r2, primask
 	str	r2, [r1, #___cpu_context_t_primask_OFFSET]
 
@@ -129,15 +120,6 @@ resume:
 	ldr	r1, [r0, #___cpu_context_t_psplim_OFFSET]
 	msr	psplim, r1
 
-	ldr	r1, [r0, #___cpu_context_t_apsr_OFFSET]
-	msr	apsr_nzcvq, r1
-
-	ldr	r1, [r0, #___cpu_context_t_ipsr_OFFSET]
-	msr	ipsr, r1
-
-	ldr	r1, [r0, #___cpu_context_t_epsr_OFFSET]
-	msr	epsr, r1
-
 	ldr	r1, [r0, #___cpu_context_t_primask_OFFSET]
 	msr	primask, r1
 

arch/arm/core/offsets/offsets_aarch32.c

@@ -86,9 +86,6 @@ GEN_OFFSET_SYM(_cpu_context_t, msp);
 GEN_OFFSET_SYM(_cpu_context_t, msplim);
 GEN_OFFSET_SYM(_cpu_context_t, psp);
 GEN_OFFSET_SYM(_cpu_context_t, psplim);
-GEN_OFFSET_SYM(_cpu_context_t, apsr);
-GEN_OFFSET_SYM(_cpu_context_t, ipsr);
-GEN_OFFSET_SYM(_cpu_context_t, epsr);
 
 GEN_OFFSET_SYM(_cpu_context_t, primask);
 GEN_OFFSET_SYM(_cpu_context_t, faultmask);

include/zephyr/arch/arm/cortex_m/cpu.h

@@ -57,9 +57,6 @@ struct __cpu_context {
 	uint32_t msplim;
 	uint32_t psp;
 	uint32_t psplim;
-	uint32_t apsr;
-	uint32_t ipsr;
-	uint32_t epsr;
 	uint32_t primask;
 	uint32_t faultmask;
 	uint32_t basepri;