soc: add npck soc driver

For npck3m8k:
1. Update code ram from 320KB to 416KB (0x1005_8000~0x100B_FFFF).
2. Update data ram from 32KB to 64KB.
3. Move fiudiv from hfcbcd1 to hfcbcd2 register

Signed-off-by: Alvis Sun <[email protected]>
Signed-off-by: Mulin Chao <[email protected]>

Author: alvsun

include/zephyr/dt-bindings/clock/npcx_clock.h

@@ -23,15 +23,16 @@
 #define NPCX_CLOCK_BUS_MCLKD       12
 
 /* clock enable/disable references */
-#define NPCX_PWDWN_CTL1            0
-#define NPCX_PWDWN_CTL2            1
-#define NPCX_PWDWN_CTL3            2
-#define NPCX_PWDWN_CTL4            3
-#define NPCX_PWDWN_CTL5            4
-#define NPCX_PWDWN_CTL6            5
-#define NPCX_PWDWN_CTL7            6
-#define NPCX_PWDWN_CTL8            7
-#define NPCX_PWDWN_CTL9            8
-#define NPCX_PWDWN_CTL_COUNT       9
+#define NPCX_PWDWN_CTL0            0
+#define NPCX_PWDWN_CTL1            1
+#define NPCX_PWDWN_CTL2            2
+#define NPCX_PWDWN_CTL3            3
+#define NPCX_PWDWN_CTL4            4
+#define NPCX_PWDWN_CTL5            5
+#define NPCX_PWDWN_CTL6            6
+#define NPCX_PWDWN_CTL7            7
+#define NPCX_PWDWN_CTL8            8
+#define NPCX_PWDWN_CTL9            9
+#define NPCX_PWDWN_CTL_COUNT       10
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ */

soc/nuvoton/npcx/Kconfig

@@ -31,6 +31,7 @@ config NPCX_IMAGE_OUTPUT_HEX
 
 config NPCX_HEADER_CHIP
 	string
+	default "npck3m8" if SOC_NPCK3M8K
 	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
 	default "npcx7m7" if SOC_NPCX7M7FC
 	default "npcx9m3" if SOC_NPCX9M3F
@@ -136,7 +137,8 @@ config NPCX_HEADER_ENABLE_FIRMWARE_CRC
 choice NPCX_HEADER_FLASH_SIZE_CHOICE
 	prompt "Flash size"
 	default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
-						  SOC_SERIES_NPCX9
+						  SOC_SERIES_NPCX9 || \
+						  SOC_SERIES_NPCK3
 	default NPCX_HEADER_FLASH_SIZE_16M
 	help
 	  This sets the SPI flash size.

soc/nuvoton/npcx/common/ecst/ecst.py

@@ -214,7 +214,7 @@ def _check_chip(output, ecst_args):
     if ecst_args.chip_name == INVALID_INPUT:
         message = f'Invalid chip name, '
         message += "should be npcx4m3, npcx4m8, npcx9m8, npcx9m7, npcx9m6, " \
-                   "npcx7m7, npcx7m6, npcx7m5."
+                   "npcx7m7, npcx7m6, npcx7m5, npck3m8k."
         _exit_with_failure_delete_file(output, message)
 
 def _set_anchor(output, ecst_args):

soc/nuvoton/npcx/common/ecst/ecst_args.py

@@ -47,6 +47,7 @@
 
 # Chips: convert from name to index.
 CHIPS_INFO = {
+    'npck3m8': {'ram_address': 0x10058000, 'ram_size': 0x68000},
     'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
     'npcx7m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
     'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},

soc/nuvoton/npcx/common/npckn/include/clock_def.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCX_CLOCK_DEF_H_
+#define _NUVOTON_NPCX_CLOCK_DEF_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/devicetree.h>
+#include <soc_clock.h>
+
+/* FMUL clock */
+#if (OFMCLK > (MAX_OFMCLK / 2))
+#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
+#else
+#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
+#endif
+
+/* APBs source clock */
+#define APBSRC_CLK OFMCLK
+
+/* AHB6 clock */
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
+#else
+#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
+#endif
+
+/* FIU clock divider */
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
+#else
+#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
+#endif
+
+#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
+#else
+#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
+#endif
+#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
+
+/* I3C clock divider */
+#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
+#define MCLKD_SL 2    /* I3C_CLK = (MCLK / 3) */
+#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
+#define MCLKD_SL 1    /* I3C_CLK = (MCLK / 2) */
+#else
+#define MCLKD_SL 0    /* I3C_CLK = MCLK */
+#endif
+
+/* Get APB clock freq */
+#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
+
+/*
+ * Frequency multiplier M/N value definitions according to the requested
+ * OFMCLK (Unit:Hz).
+ */
+#if (OFMCLK > (MAX_OFMCLK / 2))
+#define HFCGN_VAL    0x82 /* Set XF_RANGE as 1 */
+#else
+#define HFCGN_VAL    0x02
+#endif
+#if   (OFMCLK == 120000000)
+#define HFCGMH_VAL   0x0E
+#define HFCGML_VAL   0x4E
+#elif (OFMCLK == 100000000)
+#define HFCGMH_VAL   0x0B
+#define HFCGML_VAL   0xEC
+#elif (OFMCLK == 96000000)
+#define HFCGMH_VAL   0x0B
+#define HFCGML_VAL   0x72
+#elif (OFMCLK == 90000000)
+#define HFCGMH_VAL   0x0A
+#define HFCGML_VAL   0xBA
+#elif (OFMCLK == 80000000)
+#define HFCGMH_VAL   0x09
+#define HFCGML_VAL   0x89
+#elif (OFMCLK == 66000000)
+#define HFCGMH_VAL   0x07
+#define HFCGML_VAL   0xDE
+#elif (OFMCLK == 50000000)
+#define HFCGMH_VAL   0x0B
+#define HFCGML_VAL   0xEC
+#elif (OFMCLK == 48000000)
+#define HFCGMH_VAL   0x0B
+#define HFCGML_VAL   0x72
+#else
+#error "Unsupported OFMCLK Frequency"
+#endif
+
+#endif /* _NUVOTON_NPCX_CLOCK_DEF_H_ */