nrf5x_bsim: Add support for IPC/OpenAMP and split BT stack

For the 5340 simulated boards:
* Now that the HW models include the IPC and MUTEX peripherals
  we can enable them in DT.
* Also enable the DT mbox definition and allocate its shared memory
* Set the default kconfiguration for the HEAD, IPC, MBOX and split
  BT stack as in the equivalent real targets.

Signed-off-by: Alberto Escolar Piedras <[email protected]>

Author: aescolar

boards/posix/nrf_bsim/Kconfig.defconfig

@@ -42,6 +42,29 @@ config BT_CTLR
 	default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET
 	depends on BT
 
+config HEAP_MEM_POOL_SIZE
+	default 4096 if BT_RPMSG
+	default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP
+	default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET
+
+if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET
+
+config MBOX_NRFX_IPC
+	default MBOX
+
+endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET
+
+if BOARD_NRF5340BSIM_NRF5340_CPUAPP
+
+config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET
+	default y if IPC_SERVICE_BACKEND_RPMSG
+
+choice BT_HCI_BUS_TYPE
+	default BT_RPMSG
+endchoice
+
+endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP
+
 # The 15.4 driver Tx encryption is currently not functional with this
 # simulated board => we disable it by default. With this Openthread will normally
 # default to encrypt packets on its own.

boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts

@@ -46,6 +46,7 @@
 
 	chosen {
 		zephyr,flash = &flash0;
+		zephyr,bt-hci-rpmsg-ipc = &ipc0;
 	};
 
 	soc {
@@ -78,10 +79,8 @@
 			/delete-node/ pwm@24000;
 			/delete-node/ pdm@26000;
 			/delete-node/ i2s@28000;
-			/delete-node/ mbox@2a000;
 			/delete-node/ qspi@2b000;
 			/delete-node/ nfct@2d000;
-			/delete-node/ mutex@30000;
 			/delete-node/ qdec@33000;
 			/delete-node/ qdec@34000;
 			/delete-node/ usbd@36000;
@@ -97,7 +96,6 @@
 	};
 
 	/delete-node/ cpus;
-	/delete-node/ ipc;
 	/delete-node/ sw-pwm;
 };
 
@@ -118,3 +116,8 @@
 		};
 	};
 };
+
+/* We re-use the IPC shared buffer definition from the real HW. But note the start address of the
+ * buffer won't be used.
+ */
+#include <../boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi>

boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts

@@ -27,6 +27,7 @@
 	};
 
 	chosen {
+		zephyr,bt-hci-rpmsg-ipc = &ipc0;
 		zephyr,ieee802154 = &ieee802154;
 		/delete-property/ zephyr,flash-controller;
 		zephyr,flash = &flash1;
@@ -37,7 +38,6 @@
 		/delete-node/ memory@21000000;
 		/delete-node/ gpiote@4100a000;
 		/delete-node/ watchdog@4100b000;
-		/delete-node/ mbox@41012000;
 		/delete-node/ i2c@41013000;
 		/delete-node/ spi@41013000;
 		/delete-node/ uart@41013000;
@@ -48,7 +48,6 @@
 	};
 
 	/delete-node/ cpus;
-	/delete-node/ ipc;
 	/delete-node/ sw-pwm;
 };
 
@@ -75,3 +74,8 @@
 		};
 	};
 };
+
+/* We re-use the IPC shared buffer definition from the real HW. But note the start address of the
+ * buffer won't be used.
+ */
+#include <../boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi>