soc: sensry: add pinctrl

Add pin control support for the sy1xx soc.

Signed-off-by: Sven Ginka <[email protected]>

Author: tswaehn

drivers/pinctrl/CMakeLists.txt

@@ -42,5 +42,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MAX32 pinctrl_max32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCMI pinctrl_imx_scmi.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_MEC5 pinctrl_mchp_mec5.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c)
 
 add_subdirectory(renesas)

drivers/pinctrl/Kconfig

@@ -69,6 +69,7 @@ source "drivers/pinctrl/Kconfig.zynqmp"
 source "drivers/pinctrl/Kconfig.max32"
 source "drivers/pinctrl/Kconfig.mec5"
 source "drivers/pinctrl/Kconfig.wch_afio"
+source "drivers/pinctrl/Kconfig.sy1xx"
 
 rsource "renesas/Kconfig"
 

drivers/pinctrl/Kconfig.sy1xx

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 sensry.io
+
+config PINCTRL_SY1XX
+	bool "Sensry sy1xx pin controller driver"
+	default y
+	depends on DT_HAS_SENSRY_SY1XX_PINCTRL_ENABLED
+	help
+	  Sensry pin controller driver is used on sy1xx SoC series

drivers/pinctrl/pinctrl_sy1xx.c

@@ -0,0 +1,59 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2024 sensry.io
+ */
+
+#define DT_DRV_COMPAT sensry_sy1xx_pinctrl
+
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+
+#include <zephyr/arch/common/sys_io.h>
+
+static uint32_t pinctrl0_base_addr = DT_REG_ADDR(DT_NODELABEL(pinctrl));
+static uint32_t pinctrl0_base_mask = DT_REG_SIZE(DT_NODELABEL(pinctrl)) - 1;
+
+/**
+ * @brief Configure a pin.
+ *
+ * @param pin The pin to configure.
+ */
+static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
+{
+	uint32_t addr = (pin->addr & pinctrl0_base_mask) | pinctrl0_base_addr;
+
+	switch (pin->iro) {
+	case 0:
+	case 8:
+	case 16:
+	case 24:
+		/* fall through */
+		break;
+	default:
+		/* invalid inter address offset */
+		return -EINVAL;
+	}
+
+	uint32_t reg = ~(0xFFUL << pin->iro) & sys_read32(addr);
+
+	reg |= FIELD_PREP((0xFFUL << pin->iro), pin->cfg);
+	sys_write32(reg, addr);
+
+	return 0;
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		int ret = pinctrl_configure_pin(pins++);
+
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	return 0;
+}

dts/bindings/pinctrl/sensry,sy1xx-pinctrl.yaml

@@ -0,0 +1,74 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The sensry SY1xx pin controller is a single node responsible for controlling
+  pin configuration, such as pull-up, pull-down, tri-state, ...
+
+  The node has the 'pinctrl0' node label set in your SoC's devicetree,
+  so you can modify it like this:
+
+    &pinctrl0 {
+            /* your modifications go here */
+    };
+
+  For example:
+    &pinctrl0 {
+
+      /* UART0 */
+      uart0_tx: uart0_tx {
+        pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(0)>;
+      };
+
+      uart0_rx: uart0_rx {
+        pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(1)>;
+        input-enable;
+      };
+    }
+
+  Then define the uart:
+    &uart0 {
+      pinctrl-0 = <&uart0_tx &uart0_rx>;
+      pinctrl-names = "default";
+    };
+
+  Every pin configuration will be configured in a 32bit register. The configuration
+  itself is 8bit wide. So we have a number of 4 pin configurations per 32bit register.
+
+  The pinmux describes the registers address and the offset [0, 8, 16, 24] for
+  the individual configuration.
+
+  Allowed modifiers for each pin are:
+  - bias-high-impedance
+  - bias-pull-down
+  - bias-pull-up
+  - input-enable
+  - input-schmitt-enable
+
+compatible: "sensry,sy1xx-pinctrl"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+child-binding:
+  description: Each child node defines the configuration of a particular state.
+
+  include:
+    - name: pincfg-node.yaml
+      property-allowlist:
+        - bias-high-impedance
+        - bias-pull-down
+        - bias-pull-up
+        - input-enable
+        - input-schmitt-enable
+
+  properties:
+    pinmux:
+      required: true
+      type: array
+      description: |
+        Pin mux selection. See the SOC level pinctrl header
+        for a defined list of these options.

include/zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h

@@ -0,0 +1,70 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2024 sensry.io
+ */
+
+#ifndef _ZEPHYR_DT_BINDINGS_PINCTRL_SY1XX_PINCTRL_
+#define _ZEPHYR_DT_BINDINGS_PINCTRL_SY1XX_PINCTRL_
+
+#define SY1XX_PAD(pad) (pad * 8)
+
+#define SY1XX_UART0_PAD_CFG0 0x0020
+#define SY1XX_UART1_PAD_CFG0 0x0024
+#define SY1XX_UART2_PAD_CFG0 0x0028
+
+#define SY1XX_SPI0_PAD_CFG0 0x002c
+#define SY1XX_SPI0_PAD_CFG1 0x0030
+
+#define SY1XX_SPI1_PAD_CFG0 0x0034
+#define SY1XX_SPI1_PAD_CFG1 0x0038
+
+#define SY1XX_SPI2_PAD_CFG0 0x003c
+#define SY1XX_SPI2_PAD_CFG1 0x0040
+
+#define SY1XX_SPI3_PAD_CFG0 0x0044
+#define SY1XX_SPI3_PAD_CFG1 0x0048
+
+#define SY1XX_SPI4_PAD_CFG0 0x004c
+#define SY1XX_SPI4_PAD_CFG1 0x0050
+
+#define SY1XX_SPI5_PAD_CFG0 0x0054
+#define SY1XX_SPI5_PAD_CFG1 0x0058
+
+#define SY1XX_SPI6_PAD_CFG0 0x005c
+#define SY1XX_SPI6_PAD_CFG1 0x0060
+
+#define SY1XX_I2C0_PAD_CFG0 0x0100
+#define SY1XX_I2C1_PAD_CFG0 0x0104
+#define SY1XX_I2C2_PAD_CFG0 0x0108
+#define SY1XX_I2C3_PAD_CFG0 0x010c
+
+#define SY1XX_GPIO0_PAD_CFG0 0x0110
+#define SY1XX_GPIO0_PAD_CFG1 0x0114
+#define SY1XX_GPIO0_PAD_CFG2 0x0118
+#define SY1XX_GPIO0_PAD_CFG3 0x011c
+#define SY1XX_GPIO0_PAD_CFG4 0x0120
+#define SY1XX_GPIO0_PAD_CFG5 0x0124
+#define SY1XX_GPIO0_PAD_CFG6 0x0128
+#define SY1XX_GPIO0_PAD_CFG7 0x012c
+
+#define SY1XX_RGMII0_PAD_CFG0 0x0130
+#define SY1XX_RGMII0_PAD_CFG1 0x0134
+#define SY1XX_RGMII0_PAD_CFG2 0x0138
+#define SY1XX_RGMII0_PAD_CFG3 0x013c
+
+#define SY1XX_CAN0_PAD_CFG0 0x0140
+
+#define SY1XX_I2S0_PAD_CFG0 0x0144
+#define SY1XX_I2S1_PAD_CFG0 0x0148
+#define SY1XX_I2S2_PAD_CFG0 0x014c
+#define SY1XX_I2S3_PAD_CFG0 0x0150
+
+#define SY1XX_HBUS0_PAD_CFG0 0x0154
+#define SY1XX_HBUS0_PAD_CFG1 0x0158
+#define SY1XX_HBUS0_PAD_CFG2 0x015c
+#define SY1XX_HBUS0_PAD_CFG3 0x0160
+
+#define SY1XX_QSPI0_PAD_CFG0 0x0164
+#define SY1XX_QSPI0_PAD_CFG1 0x0168
+
+#endif /* _ZEPHYR_DT_BINDINGS_PINCTRL_SY1XX_PINCTRL_ */

soc/sensry/ganymed/sy1xx/common/pinctrl_soc.h

@@ -0,0 +1,72 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2024 sensry.io
+ */
+
+#ifndef GANYMED_SY1XX_PINCTRL_SOC_H
+#define GANYMED_SY1XX_PINCTRL_SOC_H
+
+#include <stdint.h>
+
+#include <zephyr/devicetree.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SY1XX_SCHMITT_ENABLE   1U
+#define SY1XX_PULL_UP_ENABLE   1U
+#define SY1XX_PULL_DOWN_ENABLE 1U
+#define SY1XX_TRISTATE_ENABLE  1U
+#define SY1XX_OUTPUT_ENABLE    1U
+
+#define SY1XX_PAD_SCHMITT_OFFS   7
+#define SY1XX_PAD_PULL_UP_OFFS   5
+#define SY1XX_PAD_PULL_DOWN_OFFS 4
+#define SY1XX_PAD_DRIVE_OFFS     2
+#define SY1XX_PAD_TRISTATE_OFFS  1
+#define SY1XX_PAD_DIR_OFFS       0
+
+/** Type for SY1XX pin. */
+typedef struct {
+	/** address of pin config register */
+	uint32_t addr;
+	/** intra register offset (8bit cfg per pin) */
+	uint32_t iro;
+	/** config for pin (8bit), describes pull-up/down, ... */
+	uint32_t cfg;
+} pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_CFG(node)                                                                        \
+	(                                                                                          \
+                                                                                                   \
+		(SY1XX_SCHMITT_ENABLE * DT_PROP(node, input_schmitt_enable))                       \
+			<< SY1XX_PAD_SCHMITT_OFFS |                                                \
+		(SY1XX_PULL_UP_ENABLE * DT_PROP(node, bias_pull_up)) << SY1XX_PAD_PULL_UP_OFFS |   \
+		(SY1XX_PULL_DOWN_ENABLE * DT_PROP(node, bias_pull_down))                           \
+			<< SY1XX_PAD_PULL_DOWN_OFFS |                                              \
+		(SY1XX_TRISTATE_ENABLE * DT_PROP(node, bias_high_impedance))                       \
+			<< SY1XX_PAD_TRISTATE_OFFS |                                               \
+		(SY1XX_OUTPUT_ENABLE & (1 - DT_PROP(node, input_enable))) << SY1XX_PAD_DIR_OFFS    \
+                                                                                                   \
+	)
+
+#define Z_PINCTRL_STATE_PIN_INIT(node, pr, idx)                                                    \
+	{                                                                                          \
+                                                                                                   \
+		.addr = DT_PROP_BY_IDX(DT_PHANDLE_BY_IDX(node, pr, idx), pinmux, 0),               \
+		.iro = DT_PROP_BY_IDX(DT_PHANDLE_BY_IDX(node, pr, idx), pinmux, 1),                \
+		.cfg = Z_PINCTRL_CFG(DT_PHANDLE_BY_IDX(node, pr, idx))                             \
+                                                                                                   \
+	},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{                                                                                          \
+		DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)                      \
+	}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GANYMED_SY1XX_PINCTRL_SOC_H */