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dts: arm64: intel: intel_socfpga_agilex: Adding device tree for i2c
Added device tree for I2C Signed-off-by: samit singh sikarwar <[email protected]>
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dts/arm64/intel/intel_socfpga_agilex.dtsi

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@@ -9,6 +9,7 @@
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
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#include <mem.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
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cpus {
@@ -188,4 +189,64 @@
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clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
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status = "disabled";
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};
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i2c0: i2c@ffc02800 {
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compatible = "snps,designware-i2c";
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reg = <0xffc02800 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@ffC02900 {
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compatible = "snps,designware-i2c";
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reg = <0xffC02900 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@ffC02A00 {
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compatible = "snps,designware-i2c";
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reg = <0xffC02A00 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@ffC02B00 {
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compatible = "snps,designware-i2c";
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reg = <0xffC02B00 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@ffC02C00 {
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compatible = "snps,designware-i2c";
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reg = <0xffC02C00 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};

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