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58 | 58 | volt-sensor0 = &vref1;
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59 | 59 | volt-sensor1 = &vbat4;
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60 | 60 | };
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| 61 | + |
| 62 | + ext_memory: memory@a0000000 { |
| 63 | + compatible = "zephyr,memory-region"; |
| 64 | + reg = <0xa0000000 DT_SIZE_M(128)>; |
| 65 | + zephyr,memory-region = "EXTMEM"; |
| 66 | + /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ |
| 67 | + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; |
| 68 | + }; |
61 | 69 | };
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62 | 70 |
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63 | 71 | <dc {
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@@ -319,9 +327,45 @@ zephyr_udc0: &usbotg_hs {
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319 | 327 | };
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320 | 328 | };
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321 | 329 |
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| 330 | +&xspi1 { |
| 331 | + clocks = <&rcc STM32_CLOCK(AHB2_2, 12U)>, |
| 332 | + <&rcc STM32_SRC_PLL2_Q HSPI_SEL(2)>; |
| 333 | + |
| 334 | + pinctrl-0 = <&hspi1_dqs0_pi2 &hspi1_ncs_ph9 |
| 335 | + &hspi1_io0_ph10 &hspi1_io1_ph11 |
| 336 | + &hspi1_io2_ph12 &hspi1_io3_ph13 |
| 337 | + &hspi1_io4_ph14 &hspi1_io5_ph15 |
| 338 | + &hspi1_io6_pi0 &hspi1_io7_pi1 |
| 339 | + &hspi1_clk_pi3>; |
| 340 | + pinctrl-names = "default"; |
| 341 | + status = "okay"; |
| 342 | + |
| 343 | + mx66lm1g45: xspi-nor-flash@0 { |
| 344 | + compatible = "st,stm32-xspi-nor"; |
| 345 | + reg = <0>; |
| 346 | + size = <DT_SIZE_M(1024)>; /* 1 Gbits */ |
| 347 | + ospi-max-frequency = <DT_FREQ_M(133)>; |
| 348 | + spi-bus-width = <XSPI_OCTO_MODE>; |
| 349 | + data-rate = <XSPI_DTR_TRANSFER>; |
| 350 | + four-byte-opcodes; |
| 351 | + status = "okay"; |
| 352 | + |
| 353 | + partitions { |
| 354 | + compatible = "fixed-partitions"; |
| 355 | + #address-cells = <1>; |
| 356 | + #size-cells = <1>; |
| 357 | + |
| 358 | + extflash_partition: partition@0 { |
| 359 | + label = "ext_storage"; |
| 360 | + reg = <0 DT_SIZE_M(128)>; |
| 361 | + }; |
| 362 | + }; |
| 363 | + }; |
| 364 | +}; |
| 365 | + |
322 | 366 | &rtc {
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323 | 367 | clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
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324 |
| - <&rcc STM32_SRC_LSE RTC_SEL(1)>; |
| 368 | + <&rcc STM32_SRC_LSE RTC_SEL(1)>; |
325 | 369 | status = "okay";
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326 | 370 | };
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327 | 371 |
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