arch/arm64: update gicv3 sre enablement

Fix writing of ICC_SRE_EL3 to or-in bits to align
with original intent to read-modify-write this
register.

Also disable FIQ and IRQ bypass so interrupt delivery
occurs through GIC.  Platforms may choose to override
this behavior in z_arm64_el3_plat_init implementations.

Remove ICC_SRE_EL3 config from viper and qemu since
this is now handled in the arm64 arch core.

Signed-off-by: Eugene Cohen <[email protected]>

Author: quic-egmc

arch/arm64/core/reset.c

@@ -89,8 +89,10 @@ void z_arm64_el3_init(void)
 
 #if defined(CONFIG_GIC_V3)
 	reg = read_sysreg(ICC_SRE_EL3);
-	reg = (ICC_SRE_ELx_SRE_BIT |	/* System register interface is used */
-	       ICC_SRE_EL3_EN_BIT);	/* Enables lower Exception level access to ICC_SRE_EL1 */
+	reg |= (ICC_SRE_ELx_DFB_BIT |	/* Disable FIQ bypass */
+		ICC_SRE_ELx_DIB_BIT |	/* Disable IRQ bypass */
+		ICC_SRE_ELx_SRE_BIT |	/* System register interface is used */
+		ICC_SRE_EL3_EN_BIT);	/* Enables lower Exception level access to ICC_SRE_EL1 */
 	write_sysreg(reg, ICC_SRE_EL3);
 #endif
 

soc/arm64/bcm_vk/viper/plat_core.c

@@ -21,11 +21,6 @@ void z_arm64_el3_plat_init(void)
 		ACTLR_EL3_CPUECTLR_BIT);
 	write_actlr_el3(reg);
 
-	reg = (ICC_SRE_ELx_DFB_BIT | ICC_SRE_ELx_DIB_BIT |
-	       ICC_SRE_ELx_SRE_BIT | ICC_SRE_EL3_EN_BIT);
-
-	write_sysreg(reg, ICC_SRE_EL3);
-
 	reg = read_sysreg(CORTEX_A72_L2ACTLR_EL1);
 	reg |= CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT;
 	write_sysreg(reg, CORTEX_A72_L2ACTLR_EL1);

soc/arm64/qemu_cortex_a53/CMakeLists.txt

@@ -2,5 +2,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
-
-zephyr_sources_ifdef(CONFIG_SOC_QEMU_CORTEX_A53    plat_core.c)