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Dat-NguyenDuykartben
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boards: s32z2xxdc2: add support PWM eMIOS
Add support PWM eMIOS for s32z2xxdc2 board. There is no LED on-board dedicated for PWM, so no sample is supported. Only enabling some pwm tests Signed-off-by: Dat Nguyen Duy <[email protected]>
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‎boards/nxp/s32z2xxdc2/doc/index.rst‎

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@@ -60,6 +60,8 @@ The boards support the following hardware features:
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+-----------+------------+-------------------------------------+
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| DSPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| eMIOS | on-chip | pwm |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml‎

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- adc
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- i2c
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- dma
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- pwm
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vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml‎

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- adc
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- i2c
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- dma
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- pwm
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vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml‎

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- adc
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- i2c
2121
- dma
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- pwm
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vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml‎

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- adc
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- i2c
2121
- dma
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- pwm
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vendor: nxp

‎tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu0.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/s32/S32Z27-BGA594-pinctrl.h>
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/ {
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aliases {
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pwm-0 = &emios0_pwm;
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};
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};
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&pinctrl {
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emios0_default: emios0_default {
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group0 {
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pinmux = <PK0_EMIOS_0_CH24_O>;
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output-enable;
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};
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};
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};
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&emios0 {
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clock-divider = <133>;
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status = "okay";
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emios0_pwm: pwm {
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pinctrl-0 = <&emios0_default>;
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pinctrl-names = "default";
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status = "okay";
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pwm_24 {
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channel = <24>;
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prescaler = <16>;
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pwm-mode = "OPWFMB";
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};
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};
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};

‎tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu1.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/s32/S32Z27-BGA594-pinctrl.h>
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/ {
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aliases {
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pwm-0 = &emios0_pwm;
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};
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};
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&pinctrl {
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emios0_default: emios0_default {
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group0 {
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pinmux = <PK0_EMIOS_0_CH24_O>;
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output-enable;
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};
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};
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};
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&emios0 {
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clock-divider = <133>;
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status = "okay";
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emios0_pwm: pwm {
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pinctrl-0 = <&emios0_default>;
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pinctrl-names = "default";
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status = "okay";
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pwm_24 {
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channel = <24>;
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prescaler = <16>;
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pwm-mode = "OPWFMB";
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};
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};
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};

‎tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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pwm_loopback_0 {
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compatible = "test-pwm-loopback";
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pwms = <&emios0_pwm 24 0 PWM_POLARITY_NORMAL>,
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<&emios0_pwm 25 0 PWM_POLARITY_NORMAL>;
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};
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};
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&pinctrl {
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emios0_default: emios0_default {
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group0 {
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pinmux = <PK0_EMIOS_0_CH24_O>;
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output-enable;
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};
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group1 {
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pinmux = <PJ15_EMIOS_0_CH25_I>;
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input-enable;
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};
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};
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};
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&emios0 {
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clock-divider = <200>;
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status = "okay";
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emios0_pwm: pwm {
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pinctrl-0 = <&emios0_default>;
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pinctrl-names = "default";
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status = "okay";
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pwm_24 {
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channel = <24>;
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prescaler = <16>;
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pwm-mode = "OPWFMB";
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};
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pwm_25 {
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channel = <25>;
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pwm-mode = "SAIC";
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prescaler = <16>;
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};
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};
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};

‎tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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pwm_loopback_0 {
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compatible = "test-pwm-loopback";
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pwms = <&emios0_pwm 24 0 PWM_POLARITY_NORMAL>,
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<&emios0_pwm 25 0 PWM_POLARITY_NORMAL>;
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};
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};
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&pinctrl {
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emios0_default: emios0_default {
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group0 {
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pinmux = <PK0_EMIOS_0_CH24_O>;
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output-enable;
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};
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group1 {
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pinmux = <PJ15_EMIOS_0_CH25_I>;
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input-enable;
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};
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};
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};
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&emios0 {
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clock-divider = <200>;
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status = "okay";
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emios0_pwm: pwm {
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pinctrl-0 = <&emios0_default>;
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pinctrl-names = "default";
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status = "okay";
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pwm_24 {
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channel = <24>;
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prescaler = <16>;
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pwm-mode = "OPWFMB";
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};
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pwm_25 {
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channel = <25>;
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pwm-mode = "SAIC";
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prescaler = <16>;
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};
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};
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};

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