tests: drivers: dma test on stm32f7 requires nocache memory

FRASTM · carlescufi · commit 82bace6e0d33 · 2023-12-22T09:53:39.000+01:00
Config the sram0 to be non-cachable to PASS the DMA testcases
chan_blen_transfer and loop_transfer
on the stm32f746zg and stm32f767zi nucleo boards.

The CONFIG_NOCACHE_MEMORY is useless as the memory region
gets the NOCACHE ATTRibutes for stm32H7 or stm32F7 as well.

Signed-off-by: Francois Ramu &lt;francois.ramu@st.com&gt;
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.conf b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.conf
@@ -1,3 +1,2 @@
 CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
 CONFIG_DMA_TRANSFER_CHANNEL_NR_1=1
-CONFIG_NOCACHE_MEMORY=y
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay
@@ -5,3 +5,8 @@
  */
 
 test_dma0: &dma2 { };
+
+/* The test driver expects the SRAM0 region to be non-cachable */
+&sram0 {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.conf b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.conf
@@ -0,0 +1,2 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=1
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay
@@ -11,3 +11,8 @@
 test_dma0: &dma2 {
 	status = "okay";
 };
+
+/* The test driver expects the SRAM0 region to be non-cachable */
+&sram0 {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.conf b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.conf
@@ -7,6 +7,3 @@ CONFIG_DMA_LOOP_TRANSFER_NUMBER_OF_DMAS=2
 # has access to this section.
 CONFIG_CODE_DATA_RELOCATION=y
 CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM4"
-
-# Required for SRAM4 to be non-cachable
-CONFIG_NOCACHE_MEMORY=y
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.conf b/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.conf
@@ -1,2 +1 @@
-CONFIG_NOCACHE_MEMORY=y
 CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay
@@ -5,3 +5,8 @@
  */
 
 test_dma0: &dma2 { };
+
+/* The test driver expects the SRAM0 region to be non-cachable */
+&sram0 {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.conf b/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.conf
@@ -1,2 +1 @@
-CONFIG_NOCACHE_MEMORY=y
 CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay
@@ -11,3 +11,8 @@
 test_dma0: &dma2 {
 	status = "okay";
 };
+
+/* The test driver expects the SRAM0 region to be non-cachable */
+&sram0 {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.conf b/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.conf
@@ -6,6 +6,3 @@ CONFIG_DMA_LOOP_TRANSFER_NUMBER_OF_DMAS=2
 # has access to this section.
 CONFIG_CODE_DATA_RELOCATION=y
 CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM4"
-
-# Required for SRAM4 to be non-cachable
-CONFIG_NOCACHE_MEMORY=y

Original file line number	Diff line number	Diff line change
`@@ -1,3 +1,2 @@`
`1`	`1`	`CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0`
`2`	`2`	`CONFIG_DMA_TRANSFER_CHANNEL_NR_1=1`
`3`		`-CONFIG_NOCACHE_MEMORY=y`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0`
	`2`	`+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=1`
Original file line number	Diff line number	Diff line change
`@@ -1,2 +1 @@`
`1`		`-CONFIG_NOCACHE_MEMORY=y`
`2`	`1`	`CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0`