drivers: clock control: Add support clock control for RX261

Add support clock control for RX261

Signed-off-by: Phi Tran <[email protected]>

Author: Phi Tran

dts/bindings/clock/renesas,rx-cgc-root-clock.yaml

@@ -43,7 +43,13 @@ properties:
     enum:
       - 0
       - 1
+      - 2
+      - 3
+      - 4
     description: |
       Drive Capacity Control (for Sub-Clock Oscillator only)
-      0: Drive capacity for standard CL.
-      1: Drive capacity for low CL.
+      0: Drive capacity for standard CL
+      1: Drive capacity for low CL (unsupported on rx261)
+      2: High-drive output for the low CL
+      3: Middle-drive output for the low CL
+      4: Low-drive output for the low CL

include/zephyr/drivers/clock_control/renesas_rx_cgc.h

@@ -17,6 +17,16 @@
 		    (UTIL_CAT(RX_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))),        \
 		    (RX_CLOCKS_CLOCK_DISABLED))
 
+#define RX_IF_CLK_SRC(node_id)                                                                     \
+	COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay),\
+			(UTIL_CAT(RX_IF_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))),\
+			(RX_CLOCKS_CLOCK_DISABLED))
+
+#define RX_LPT_CLK_SRC(node_id)                                                                    \
+	COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay),\
+			(UTIL_CAT(RX_LPT_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))),\
+			(RX_LPT_CLOCKS_NON_USE))
+
 struct clock_control_rx_pclk_cfg {
 	const struct device *clock_src_dev;
 	uint32_t clk_div;

include/zephyr/dt-bindings/clock/rx_clock.h

@@ -14,6 +14,16 @@
 #define RX_CLOCKS_SOURCE_PLL            4
 #define RX_CLOCKS_SOURCE_CLOCK_DISABLE  0xff
 
+#define RX_IF_CLOCKS_SOURCE_CLOCK_HOCO 0
+#define RX_IF_CLOCKS_SOURCE_CLOCK_LOCO 2
+#define RX_IF_CLOCKS_SOURCE_PLL        5
+#define RX_IF_CLOCKS_SOURCE_PLL2       6
+
+#define RX_LPT_CLOCKS_SOURCE_CLOCK_SUBCLOCK       0
+#define RX_LPT_CLOCKS_SOURCE_CLOCK_IWDT_LOW_SPEED 1
+#define RX_LPT_CLOCKS_NON_USE                     2
+#define RX_LPT_CLOCKS_SOURCE_CLOCK_LOCO           3
+
 #define RX_PLL_MUL_4   7
 #define RX_PLL_MUL_4_5 8
 #define RX_PLL_MUL_5   9