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| 1 | +/* |
| 2 | + * Copyright (c) 2025 STMicroelectronics. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | +/* |
| 7 | + * STM32WB0 Deepstop implementation for Power Management framework |
| 8 | + * |
| 9 | + * TODO: |
| 10 | + * - document the control flow on PM transitions |
| 11 | + * - assertions around system configuration |
| 12 | + * (e.g., valid slow clock selected, RTC enabled, ...) |
| 13 | + * - ... |
| 14 | + */ |
| 15 | +#include <zephyr/kernel.h> |
| 16 | +#include <zephyr/pm/pm.h> |
| 17 | +#include <zephyr/sys_clock.h> |
| 18 | +#include <zephyr/init.h> |
| 19 | +#include <zephyr/arch/common/pm_s2ram.h> |
| 20 | + |
| 21 | +/* Private headers in zephyr/drivers/... */ |
| 22 | +#include <clock_control/clock_stm32_ll_common.h> |
| 23 | + |
| 24 | +#include <soc.h> |
| 25 | +#include <stm32_ll_pwr.h> |
| 26 | +#include <stm32_ll_rcc.h> |
| 27 | +#include <stm32_ll_cortex.h> |
| 28 | +#include <stm32_ll_system.h> |
| 29 | + |
| 30 | +#include <zephyr/logging/log.h> |
| 31 | +LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); |
| 32 | + |
| 33 | +#if defined(CONFIG_SOC_STM32WB05XX) || defined(CONFIG_SOC_STM32WB09XX) |
| 34 | +#define HAS_GPIO_RETENTION 1 |
| 35 | +#else |
| 36 | +#define HAS_GPIO_RETENTION 0 |
| 37 | +#endif /* CONFIG_SOC_STM32WB05XX || CONFIG_SOC_STM32WB09XX */ |
| 38 | + |
| 39 | +/* System-level state managed by PM callbacks |
| 40 | + * Things that need to be preserved across Deepstop, but |
| 41 | + * have no associated driver to backup and restore them. |
| 42 | + */ |
| 43 | +#define STM32WB0_SRAM DT_CHOSEN(zephyr_sram) |
| 44 | +#define STM32WB0_BL_STACK_SIZE (20 * 4) /* in bytes */ |
| 45 | +#define STM32WB0_BL_STACK_TOP ((void *)(DT_REG_ADDR(STM32WB0_SRAM) + DT_REG_SIZE(STM32WB0_SRAM) \ |
| 46 | + - STM32WB0_BL_STACK_SIZE)) |
| 47 | + |
| 48 | +static uint8_t bl_stk_area_backup[STM32WB0_BL_STACK_SIZE]; |
| 49 | +static uint32_t rcc_apb1enr_vr, rcc_ahbenr_vr; |
| 50 | + |
| 51 | +/* Callback for arch_pm_s2ram_suspend */ |
| 52 | +static int suspend_system_to_deepstop(void) |
| 53 | +{ |
| 54 | + /* Enable SLEEPDEEP to allow entry in Deepstop */ |
| 55 | + LL_LPM_EnableDeepSleep(); |
| 56 | + |
| 57 | + /* Complete all memory transactions */ |
| 58 | + __DSB(); |
| 59 | + |
| 60 | + |
| 61 | + /* Attempt entry in Deepstop */ |
| 62 | + __WFI(); |
| 63 | + |
| 64 | + /* Make sure no meaningful instruction is |
| 65 | + * executed during the two cycles latency |
| 66 | + * it takes to power-gate the CPU. |
| 67 | + */ |
| 68 | + __NOP(); |
| 69 | + __NOP(); |
| 70 | + |
| 71 | + /* This code is reached only if the device did not |
| 72 | + * enter Deepstop mode (e.g., because an interrupt |
| 73 | + * became pending during preparatory work). |
| 74 | + * Disable SLEEPDEEP and return the appropriate error. |
| 75 | + */ |
| 76 | + LL_LPM_EnableSleep(); |
| 77 | + |
| 78 | + return -EBUSY; |
| 79 | +} |
| 80 | + |
| 81 | +/* Backup system state to save and configure power |
| 82 | + * controller before entry in Deepstop mode |
| 83 | + */ |
| 84 | +static void prepare_for_deepstop_entry(void) |
| 85 | +{ |
| 86 | + /* DEEPSTOP2 configuration is performed in familiy-wide code |
| 87 | + * instead of here (see `soc/st/stm32/common/soc_config.c`). |
| 88 | + * RAMRET configuration is performed once during SoC init, |
| 89 | + * since it is retained across Deepstop (see `soc.c`). |
| 90 | + */ |
| 91 | + |
| 92 | + /* Save the clock configuration. */ |
| 93 | + rcc_apb1enr_vr = RCC->APB1ENR; |
| 94 | + rcc_ahbenr_vr = RCC->AHBENR; |
| 95 | + |
| 96 | + /* Clear wakeup reason flags (which inhibit Deepstop) */ |
| 97 | + LL_PWR_ClearWakeupSource(LL_PWR_WAKEUP_ALL); |
| 98 | + LL_SYSCFG_PWRC_ClearIT(LL_SYSCFG_PWRC_WKUP); |
| 99 | + LL_PWR_ClearDeepstopSeqFlag(); |
| 100 | + LL_PWR_EnableWU_EWBLEHCPU(); |
| 101 | + |
| 102 | +#if HAS_GPIO_RETENTION |
| 103 | + /* Enable GPIO state retention in Deepstop if available. |
| 104 | + * Do not enable this if low-power mode debugging has been |
| 105 | + * enabled via Kconfig, because it prevents the debugger |
| 106 | + * from staying connected to the SoC. |
| 107 | + */ |
| 108 | + if (!IS_ENABLED(CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP)) { |
| 109 | + LL_PWR_EnableGPIORET(); |
| 110 | + LL_PWR_EnableDBGRET(); |
| 111 | + } |
| 112 | +#endif /* HAS_GPIO_RETENTION */ |
| 113 | + |
| 114 | + /* The STM32WB0 bootloader uses the end of SRAM as stack. |
| 115 | + * Since it is executed on every reset, including wakeup |
| 116 | + * from Deepstop, any data placed at the end of SRAM would |
| 117 | + * be corrupted. |
| 118 | + * Backup these words for later restoration to avoid data |
| 119 | + * corruption. A much better solution would be to mark this part |
| 120 | + * of SRAM as unusable, but no easy solution was found to |
| 121 | + * achieve this. |
| 122 | + */ |
| 123 | + memcpy(bl_stk_area_backup, STM32WB0_BL_STACK_TOP, STM32WB0_BL_STACK_SIZE); |
| 124 | +} |
| 125 | + |
| 126 | +/* Restore SoC-level configuration lost in Deepstop |
| 127 | + * This function must be called right after wakeup. |
| 128 | + */ |
| 129 | +static void post_resume_configuration(void) |
| 130 | +{ |
| 131 | + __ASSERT_NO_MSG(LL_PWR_GetDeepstopSeqFlag() == 1); |
| 132 | + |
| 133 | + /* VTOR has been reset to its default value: restore it. |
| 134 | + * (Note that RAM_VR.AppBase was filled during SoC init) |
| 135 | + */ |
| 136 | + SCB->VTOR = RAM_VR.AppBase; |
| 137 | + |
| 138 | + /* Restore the clock configuration. */ |
| 139 | + RCC->AHBENR = rcc_ahbenr_vr; |
| 140 | + RCC->APB1ENR = rcc_apb1enr_vr; |
| 141 | + |
| 142 | + /* Restore bootloader stack area */ |
| 143 | + memcpy(STM32WB0_BL_STACK_TOP, bl_stk_area_backup, STM32WB0_BL_STACK_SIZE); |
| 144 | +} |
| 145 | + |
| 146 | +/* Power Management subsystem callbacks */ |
| 147 | +void pm_state_set(enum pm_state state, uint8_t substate_id) |
| 148 | +{ |
| 149 | + /* Ignore substate: STM32WB0 has only one low-power mode */ |
| 150 | + ARG_UNUSED(substate_id); |
| 151 | + |
| 152 | + if (state != PM_STATE_SUSPEND_TO_RAM) { |
| 153 | + |
| 154 | + /* Deepstop is a suspend-to-RAM state. |
| 155 | + * Something is wrong if a different |
| 156 | + * power state has been requested. |
| 157 | + */ |
| 158 | + LOG_ERR("Unsupported power state %u", state); |
| 159 | + } |
| 160 | + |
| 161 | + prepare_for_deepstop_entry(); |
| 162 | + |
| 163 | + /* Select Deepstop low-power mode and suspend system */ |
| 164 | + LL_PWR_SetPowerMode(LL_PWR_MODE_DEEPSTOP); |
| 165 | + |
| 166 | + if (arch_pm_s2ram_suspend(suspend_system_to_deepstop) >= 0) { |
| 167 | + |
| 168 | + /* Restore system configuration only if the SoC actually |
| 169 | + * entered Deepstop - otherwise, no state has been lost |
| 170 | + * and it would be a waste of time to do so. |
| 171 | + */ |
| 172 | + post_resume_configuration(); |
| 173 | + } |
| 174 | +} |
| 175 | + |
| 176 | +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) |
| 177 | +{ |
| 178 | + ARG_UNUSED(state); |
| 179 | + ARG_UNUSED(substate_id); |
| 180 | + |
| 181 | + /* We restore system state in @ref{post_resume_configuration}. |
| 182 | + * The only thing we may have to do is release GPIO retention, |
| 183 | + * which we have not done yet because we wanted the driver to |
| 184 | + * restore all configuration first. |
| 185 | + * We also need to enable IRQs to fullfill the API contract. |
| 186 | + */ |
| 187 | +#if HAS_GPIO_RETENTION |
| 188 | + LL_PWR_DisableGPIORET(); |
| 189 | + LL_PWR_DisableDBGRET(); |
| 190 | +#endif /* HAS_GPIO_RETENTION */ |
| 191 | + |
| 192 | + __enable_irq(); |
| 193 | +} |
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