m2gl025_miv: Adjust frequencies and performance

The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.

Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.

The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.

To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.

This commit fixes #31726.

Signed-off-by: Adam Jeliński <[email protected]>

Author: ajelinski

boards/riscv/m2gl025_miv/support/m2gl025_miv.repl

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: Apache-2.0
+
+using "platforms/cpus/miv.repl"
+
+uart:
+    clockFrequency: 4000000
+
+clint:
+    frequency: 4000000
+
+timer0:
+    clockFrequency: 4000000
+
+timer1:
+    clockFrequency: 4000000

boards/riscv/m2gl025_miv/support/m2gl025_miv.resc

@@ -5,10 +5,10 @@ $name?="Mi-V"
 
 using sysbus
 mach create $name
-machine LoadPlatformDescription @platforms/boards/miv-board.repl
+machine LoadPlatformDescription $ORIGIN/m2gl025_miv.repl
 
 showAnalyzer uart
-cpu PerformanceInMips 80
+cpu PerformanceInMips 4
 
 macro reset
 """

soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series

@@ -6,7 +6,7 @@ config SOC_SERIES
 	default "miv"
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 660000
+	default 4000000
 
 config RISCV_SOC_INTERRUPT_INIT
 	default y