drivers: entropy: stm32: Check clock config at runtime

RNG clock configuration constraints differ between each series.
Rather than providing complex build time code to verify RNG clock
configuration is correct, take advantage of CECS bit (Clock error
current status) to assess clock configuration.

This check is implemented under a specific ENTROPY_STM32_CLK_CHECK
Kconfig option. This allows user to disable this feature in specific
conditions:
- CED bit disabled in application (in which case CECS status is not valid)
- Clock configuration is deemed as correct by user. Note that RNG number
  are always generated, whatever the clock status.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

drivers/entropy/Kconfig.stm32

@@ -53,4 +53,15 @@ config ENTROPY_STM32_ISR_THRESHOLD
 	  buffer goes below this number hardware entropy generation will be
 	  started.
 
+config ENTROPY_STM32_CLK_CHECK
+	bool "Runtime clock configuration check"
+	default y
+	help
+	  Enables a check on RNG clock configuration. Correct clock
+	  configuration depends on STM32 series. Check reference manual if an
+	  error is reported.
+	  This check assumes CED (Clock Error Detected) bit is enabled (when
+	  available, CED is enabeld by default). Disable this check if CED is
+	  disabled.
+
 endif # ENTROPY_STM32_RNG

drivers/entropy/entropy_stm32.c

@@ -233,6 +233,11 @@ static int random_byte_get(void)
 	unsigned int key;
 	RNG_TypeDef *rng = entropy_stm32_rng_data.rng;
 
+	if (IS_ENABLED(CONFIG_ENTROPY_STM32_CLK_CHECK)) {
+		__ASSERT(LL_RNG_IsActiveFlag_CECS(rng) == 0,
+			 "Clock configuration error. See reference manual");
+	}
+
 	key = irq_lock();
 
 	if (LL_RNG_IsActiveFlag_SEIS(rng) && (recover_seed_error(rng) < 0)) {
@@ -578,27 +583,6 @@ static int entropy_stm32_rng_init(const struct device *dev)
 	__ASSERT_NO_MSG(dev_data != NULL);
 	__ASSERT_NO_MSG(dev_cfg != NULL);
 
-#if (DT_INST_NUM_CLOCKS(0) == 1)
-	/* No domain clock selected, let's check that the configuration is correct */
-
-#if defined(CONFIG_SOC_SERIES_STM32L0X) && \
-	(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC * STM32_PLL_MULTIPLIER) != MHZ(96)
-	/* PLL used as RNG clock source (default), but its frequency doesn't fit */
-	/* Fix PLL freq or select HSI48 as RNG clock source */
-#warning PLL clock not properly configured to be used as RNG clock. Configure another clock.
-#elif !DT_NODE_HAS_COMPAT(DT_NODELABEL(clk_hsi48), fixed_clock)
-	/* No HSI48 available, a specific RNG domain clock has to be selected */
-#warning RNG domain clock not configured
-#endif
-
-#if DT_NODE_HAS_COMPAT(DT_NODELABEL(clk_hsi48), fixed_clock)  && !STM32_HSI48_ENABLED
-	/* On these series, HSI48 is available and set by default as RNG clock source */
-	/* HSI48 clock not enabled */
-#warning HSI48 clock should be enabled or other domain clock selected
-#endif
-
-#endif /* (DT_INST_NUM_CLOCKS(0) == 1) */
-
 	dev_data->clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
 
 	if (!device_is_ready(dev_data->clock)) {